Integrated circuit printhead for an ink jet printer including an integrated identification circuit

• US 5,363,134 A
• Filed: 05/20/1992
• Issued: 11/08/1994
• Est. Priority Date: 05/20/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: HP Inc.
• Inventors: Badyal, Rajeev, Allen, Ross R., Barbehenn, George, Hulings, James R., Saunders, Michael B.
• Primary Examiner(s): Fuller, Benjamin R.
• Assistant Examiner(s): BARLOW JR, JOHN E
• Application Number:
  US07/886,641
• Time in Patent Office: 902 Days
• Field of Search: 346/140 R, 346/1.1, 400/175, 307/449
• US Class Current: 347/49
• CPC Class Codes: B41J 2/04506 aiming at correcting manufacturing tolerances
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/0458 controlling heads based on heating elements forming bubbles
• CPC Class Codes: B41J 2/175 Ink supply systems ; Circuit parts therefor
• CPC Class Codes: B41J 2/17546 electronically
• CPC Class Codes: B41J 2202/17 Readable information on the head
• CPC Class Codes: G06K 19/07 with integrated circuit chips

Abstract

An integrated circuit for use in the printhead of an ink jet printer includes an array circuit for heating an ink reservoir to produce a pattern of ink jets, the array circuit including a plurality of resistor cells arranged into rows and columns. A corresponding number of row and column lines are coupled to the integrated circuit array for selecting and energizing the resistor cells according to the desired printing pattern. An identification circuit integrated into the same substrate as the array circuit includes one or more programmable paths, the programmable paths corresponding and coupled to each row line. The programmable paths each include the serial combination of a programmable fuse and an active device. The opposite end of the programmable paths are coupled together at a common node, which in turn is coupled to an output circuit for providing a single output signal in response to a polling of the row lines. The identification circuit can be programmed and polled without adversely affecting or energizing the array circuit.

Claims

1. An integrated circuit for use in thermal ink jet printheads for providing identifiable characteristics of individual print cartridges containing such a printhead to a printhead controller, comprising:

an array circuit heating an ink reservoir to produce a pattern of ink jets, the array circuit including a plurality of resistor cells arranged in a predetermined number of rows and columns;

a plurality of row and column lines coupled to the array circuit for selectively driving at least one of the resistor cells; and

an identification circuit including a plurality of programmable paths, at least one of the programmable paths corresponding and coupled to each row line at a first end of the programmable paths and coupled at a second end of the programmable paths to a common node.

2. A circuit as in claim 1 in which the identification circuit further comprises an output means having an input coupled to the common node and an output for providing an output signal in response to a polling of the row lines by said printhead controller.

3. A circuit as in claim 2 in which the output means comprises:

a resistor coupled to the common node; and

a transistor having a control node coupled to the common node and a controlled node forming the output.

4. A circuit as in claim 3 in which the output is coupled to a thermal resistor divider, wherein

the output provides circuit temperature information within a first voltage range and

the output provides an output signal in response to the polling of the address lines within a second voltage range.

5. A circuit as in claim 1 in which the programmable paths each comprise the serial combination of a programmable fuse and an active device.

6. A circuit as in claim 5 in which the programmable fuse is selected from the group consisting of a fusible polysilicon link, a fusible NiCr link, and a fusible metal link.

7. A circuit as in claim 5 in which the active device comprises a diode.

8. A circuit as in claim 5 in which the active device comprises a field-effect transistor.

9. A circuit as in claim 1 in which the resistor cells further comprise a field-effect transistor for controlling current flow through the resistor cell.

10. An integrated circuit for use in thermal ink jet printheads for providing identifiable characteristics of individual print cartridges containing such a printhead to a printhead controller, comprising:

an array circuit for heating an ink reservoir to produce a pattern of ink jets, the array circuit including a plurality of actively controlled resistor cells arranged in a predetermined number of rows and columns;

a plurality of row and column lines coupled to the array circuit for selectively driving at least one of the resistor cells;

an identification circuit including a plurality of programmable paths, a first end of each programmable path being coupled to a respective row line, a second end of each programmable path being coupled together to form a common node; and

an output means having an input coupled to the common node and an output for providing an output signal in response to a polling of the row lines, the output signal being multiplexed onto an existing interconnect pad of the printhead.

11. A method for identifying characteristics of an integrated circuit thermal ink jet printhead, having an array circuit for heating an ink reservoir to produce a pattern of ink jets, the array circuit including a plurality of resistor cells arranged in a predetermined number of rows and columns and a plurality of row and column lines coupled to the array circuit for selectively driving at least one of the resistor cells, the method comprising the steps of:

providing at least one programmable path coupled to each row line; and

programming the programmable paths according to a predetermined pattern indicative of the characteristics of the printhead by;

(a) forming a short-circuit path in response to a first logic state for passing a signal current; and

(b) forming an open-circuit path in response to a second logic state for blocking the flow of a signal current.

12. The method of claim 11 further comprising the steps of:

polling each row line, the polling causing a signal current to flow through the programmable path in a first logic state and no current to flow through the programmable path in a second logic state; and

combining the signal currents of the programmable paths to form a single output identification signal.

13. The method of claim 12 further comprising the step of multiplexing the output identification signal onto an existing interconnection pad of the printhead.

14. The method of claim 12 further comprising the steps of:

providing a thermal resistor divider for generating an analog voltage related to temperature at an interconnection pad within a first voltage range; and

coupling the output identification signal to the interconnection pad for providing an identification signal within a second voltage range.

15. The method of claim 11 further comprising the steps of:

coupling a first programmable path to each row line to form a first group of programmable paths; and

coupling a second programmable path to each row line to form a second group of programmable paths.

16. The method of claim 15 further comprising the steps of:

programming the programmable paths according to a predetermined pattern;

polling each row line, the polling causing a signal current to flow through the programmable path in a first logic state and no current to flow through the programmable path in a second logic state;

combining the signal currents of the programmable paths in the first group to form a first output identification signal; and

combining the signal currents of the programmable paths in the second group to form a second output identification signal.

17. The method of claim 16 further comprising the step of multiplexing the first and second output identification signals to form a single output identification signal.