Highly stable asymmetric SRAM cell
First Claim
1. An asymmetric static random access memory cell, comprising:
- a first load element having a first terminal connected to a first power supply voltage terminal, and a second terminal;
a second load element having a first terminal connected to the first power supply voltage terminal, and a second terminal;
a first pull-down transistor having a first current electrode coupled to the second terminal of the first load element, a second current electrode coupled to a second power supply voltage terminal, and a control electrode;
a second pull-down transistor having a first current electrode coupled to the second terminal of the second load element, a second current electrode coupled to the second power supply voltage terminal, and a control electrode;
a first coupling transistor having a first current electrode coupled to the first current electrode of the second pull-down transistor, a control electrode, and a second current electrode, the first coupling transistor having a first channel width; and
a second coupling transistor having a first current electrode coupled to the first current electrode of the first pull-down transistor, a control electrode, and a second current electrode, the second coupling transistor having a second channel width;
wherein the first channel width is less than the second channel width.
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Accused Products
Abstract
An asymmetric static random access memory cell (50 and 53) includes polysilicon load elements (55 and 56), N-channel pull-down transistors (57 and 58), and N-channel coupling transistors (59 and 60). One of the coupling transistors (59 and 81) has a channel width that is less than the channel width of the other coupling transistor (60 and 80). The asymmetric cells (50 and 53) are located close to power supply voltage terminal VSS, while conventional symmetrical cells (51 and 52) are located apart from the power supply voltage terminal VSS. The asymmetric cells (50 and 53) correct an imbalance in the ground path caused by a parasitic resistance (83 and 86) of a diffusion layer (94) that is used to couple the asymmetric cells (50 and 53) to ground potential. The asymmetric cell (50 and 53) improves cell stability without degrading performance or increasing cell area.
34 Citations
16 Claims
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1. An asymmetric static random access memory cell, comprising:
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a first load element having a first terminal connected to a first power supply voltage terminal, and a second terminal; a second load element having a first terminal connected to the first power supply voltage terminal, and a second terminal; a first pull-down transistor having a first current electrode coupled to the second terminal of the first load element, a second current electrode coupled to a second power supply voltage terminal, and a control electrode; a second pull-down transistor having a first current electrode coupled to the second terminal of the second load element, a second current electrode coupled to the second power supply voltage terminal, and a control electrode; a first coupling transistor having a first current electrode coupled to the first current electrode of the second pull-down transistor, a control electrode, and a second current electrode, the first coupling transistor having a first channel width; and a second coupling transistor having a first current electrode coupled to the first current electrode of the first pull-down transistor, a control electrode, and a second current electrode, the second coupling transistor having a second channel width; wherein the first channel width is less than the second channel width. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An asymmetric static random access memory cell, comprising:
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a first load element having a first terminal connected to a first power supply voltage terminal, and a second terminal; a second load element having a first terminal connected to the first power supply voltage terminal, and a second terminal; a first pull-down transistor having a first current electrode coupled to the second terminal of the first load element, a second current electrode coupled to a second power supply voltage terminal, and a control electrode; a second pull-down transistor having a first current electrode coupled to the second terminal of the second load element, a second current electrode coupled to the second power supply voltage terminal, and a control electrode; a first coupling transistor having a first current electrode coupled to the first current electrode of the second pull-down transistor, a control electrode, and a second current electrode, the first coupling transistor having a first channel width-to-channel length ratio; and a second coupling transistor having a first current electrode coupled to the first current electrode of the first pull-down transistor, a control electrode, and a second current electrode, the second coupling transistor having a second channel width-to-channel length ratio; wherein the first channel width-to-channel length ratio being less than the second channel width-to-channel length ratio. - View Dependent Claims (8, 9, 10, 11)
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12. A static random access memory array, comprising:
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a plurality of words lines; a plurality of bit line pairs arranged to intersect the plurality of word lines; a power supply voltage terminal; a first plurality of static random access memory cells coupled to the power supply voltage terminal, a memory cell of the first plurality of static random access memory cells having a first storage node coupled to a first bit line of a first bit line pair by a first coupling transistor, and a second storage node coupled to a second bit line of the first bit line pair by a second coupling transistor, a channel width of the first coupling transistor being different than a channel width of the second coupling transistor; and a second plurality of static random access memory cells coupled to the power supply voltage terminal, a memory cell of the second plurality of static random access memory cells having a first storage node coupled to a first bit line of a second bit line pair by a third coupling transistor, and second storage node coupled to a second bit line of the second bit line pair by a fourth coupling transistor, a channel width of the third coupling transistor being substantially equal to a channel width of the fourth coupling transistor - View Dependent Claims (13, 14, 15, 16)
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Specification