Nonvolatile memory with automatic power supply configuration

• US 5,363,335 A
• Filed: 09/28/1993
• Issued: 11/08/1994
• Est. Priority Date: 09/28/1993
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Price, Thomas C., Jungroth, Owen
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/127,943
• Time in Patent Office: 406 Days
• Field of Search: 365/226, 365/189.09, 365/228, 365/227, 365/900, 307/296.01, 307/296.08
• US Class Current: 365/226
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A nonvolatile memory is described that includes a memory array and control circuitry coupled to the memory array for controlling memory operations with respect to the memory array. The control circuitry can operate at a first power supply voltage and a second power supply voltage. A configuration circuit is coupled to receive a power supply voltage indication signal for selectively configuring the control circuitry in accordance with the power supply indication signal to operate at one of the first and second power supply voltages. When the power supply voltage indication signal is in a first state, the configuration circuit configures the control circuitry to operate at the first power supply voltage. When the power supply voltage indication signal is in a second state, the configuration circuit configures the control circuitry to operate at the second power supply voltage. A method for automatically configuring a nonvolatile memory with respect to the voltage level of a power supply applied to the nonvolatile memory is also described. The power supply can be in a first voltage level and a second voltage level.

Claims

1. A nonvolatile memory, comprising:

(A) a memory array;

(B) control circuitry having a boost circuit and coupled to the memory array for controlling memory operations with respect to the memory array, wherein the control circuitry can operate at either a first power supply voltage or a second power supply voltage;

(C) a power supply configuration circuit coupled to receive a power supply voltage indication signal for selectively configuring the control circuitry in accordance with the power supply indication signal to operate at one of the first and second power supply voltages that is applied to the control circuitry, wherein when the power supply voltage indication signal is in a first state, the configuration circuit configures the control circuitry to operate at the first power supply voltage, wherein when the power supply voltage indication signal is in a second state, the configuration circuit figures the control circuitry to operate at the second power supply voltage;

(D) an input pin coupled to the configuration circuit for receiving the power supply voltage indication signal and for applying the power supply voltage indication signal to the configuration circuit;

(E) a detection circuit for determining which one of the first and second power supply voltages is applied to the nonvolatile memory and for generating the power supply voltage indication signal accordingly, wherein when the detection circuit determines that the first power supply voltage is applied to the nonvolatile memory, the power supply voltage indication signal generated by the detection circuit is in the first state, wherein when the detection circuit determines that the second power supply voltage is applied to the nonvolatile memory, the power supply voltage indication signal generated by the detection circuit is in the second state.

4. The nonvolatile memory of claim 1, wherein the first power supply voltage is approximately 5 volts and the second power supply voltage is approximately 3.3 volts.

5. The nonvolatile memory of claim 1, wherein the nonvolatile memory includes memory cells that are electrically programmable and erasable.

6. The nonvolatile memory of claim 1, wherein the control circuitry can operate at a plurality of power supply voltages, including the first and second power supply voltages, wherein the configuration circuit can configure the control circuitry to operate at one of the plurality of power supply voltages at one time.

2. A nonvolatile memory, comprising;

(A) a memory array;

(B) control circuitry coupled to the memory array for controlling memory operations with respect to the memory array, wherein the control circuitry can operate at either a first power supply voltage or a second power supply voltage;

(C) a power supply configuration circuit coupled to receive a power supply voltage indication signal for selectively configuring the control circuitry in accordance with the power supply indication signal to operate at one of the first and second power supply voltages that is applied to the control circuitry, wherein when the power supply voltage indication signal is in a first state. the configuration circuit configures the control circuitry to operate at the first power supply voltage, wherein when the power supply voltage indication signal is in a second state, the configuration circuit configures the control circuitry to operate at the second power supply voltage;

(D) an input pin coupled to the configuration circuit for receiving the power supply voltage indication signal from an external circuit and for applying the power supply voltage indication signal to the configuration circuit;

wherein the control circuitry further comprises

(i) a plurality of input buffers, each having a first device size ratio for a trip DO. jet associated with the first power supply voltage and a second device size ratio for the trip point associated with the second power supply voltage;

(ii) a plurality of output buffers, each having an output compensation circuit;

(iii) a boost circuit coupled to a selected word line of the memory array via a decoder;

(iv) a memory operation control engine for controlling the memory operations with respect to the memory array, wherein the memory operation control engine includes a first memory operation control algorithm associated with the first power supply voltage and a second memory operation control algorithm associated with the second power supply voltage, wherein when the power supply voltage indication signal is in the first state, the configuration circuit (1) causes each of the plurality of input buffers to have the first device size ratio, (2) disables the output compensation circuit in each of the plurality of output buffers, (3) causes the boost circuit to boost the first power supply voltage applied to the selected word line of the memory array during a read operation to the second power supply voltage, and (4) causes the memory operation control engine to select the first memory operation control algorithm, wherein when the power supply voltage indication signal is in the second state, the configuration circuit (5) causes each of the plurality of input buffers to have the second device size ratio, (6) enables the output compensation circuit in each of the plurality of output buffers, (7) disables the boost circuit, and (8) causes the memory operation control engine to select the second memory operation control algorithm.

3. A nonvolatile memory, comprising;

(A) a memory array;

(B) control circuitry having a boost circuit and coupled to the memory array for controlling memory operations with respect to the memory array. wherein the control circuitry can operate at either a first power supply voltage or a second power supply voltage;

(C) a power supply configuration circuit coupled to receive a power supply voltage indication signal for selectively configuring the control circuitry in accordance with the power supply indication signal to at one and second power supply voltages that is applied to the control circuitry, wherein when the power supply voltage indication signal is in a first state. the configuration circuit configures the control circuitry to operate at the first power supply voltage, wherein when the power supply voltage indication signal is in a second state, the configuration circuit configuration to control circuitry to operate at the second power supply voltage;

(D) an input pin coupled to the configuration circuit for receiving the power supply voltage indication signal from an external circuit and for applying the power supply voltage indication signal to the configuration circuit;

(E) a configuration memory coupled to the configuration circuit for storing configuration information to configure the configuration circuit to operate with respect to the power supply voltage indication signal, wherein the configuration memory can be in a first configuration state, a second configuration state, and a third configuration state, wherein when the configuration memory is in the first configuration state, the configuration circuit configures the control circuitry to operate in accordance with the power supply voltage indication signal, wherein when the configuration memory is in the second configuration state, the configuration circuit configures the control circuitry to operate at the first power supply voltage regardless of the power supply voltage indication signal, wherein when the configuration memory is in the third configuration state, the configuration circuit configures the control circuitry to operate at the second power supply voltage regardless of the power supply voltage indication signal.

7. A nonvolatile memory, comprising:

(A) a memory array;

(B) control circuitry coupled to the memory array for controlling memory operations with respect to the memory array, wherein the control circuitry can operate at either a first power supply voltage or a second power supply voltage, wherein the control circuitry further comprises

(i) a plurality of input buffers, each having a first device size ratio for a trip point associated with the first power supply voltage and a second device size ratio for the trip point associated with the second power supply voltage;

(ii) a plurality of output buffers, each having an output compensation circuit;

(iii) a boost circuit coupled to a selected word line of the memory array via a decoder;

(iv) a memory operation control engine for controlling the memory operations with respect to the memory array, wherein the memory operation control engine includes a first memory operation control algorithm associated with the first power supply voltage and a second memory operation control algorithm associated with the second power supply voltage;

(C) a configuration circuit coupled to receive a power supply voltage indication signal for selectively configuring the control circuitry in accordance with the power supply voltage indication signal to operate at one of the first and second power supply voltages that is applied to the control circuitry, wherein when the power supply voltage indication signal is in a first state, the configuration circuit (1) causes each of the plurality of input buffers to have the first device size ratio, (2) disables the output compensation circuit in each of the plurality of output buffers, (3) causes the boost circuit to boost the first power supply voltage applied to the selected word line of the memory array during a read operation to the second power supply voltage, and (4) causes the memory operation control engine to select the first memory operation control algorithm, wherein when the power supply voltage indication signal is in a second state, the configuration circuit (5) causes each of the plurality of input buffers to have the second device size ratio, (6) enables the output compensation circuit in each of the plurality of output buffers, (7) disables the boost circuit, and (8) causes the memory operation control engine to select the second memory operation control algorithm.

8. The nonvolatile memory of claim 7, further comprising an input pin coupled to the configuration circuit for receiving the power supply voltage indication signal from an external circuit and for applying the power supply voltage indication signal to the configuration circuit.

9. The nonvolatile memory of claim 7, further comprising a detection circuit for determining which one of the first and second power supply voltages is applied to the nonvolatile memory and for generating the power supply voltage indication signal accordingly, wherein when the detection circuit determines that the first power supply voltage is applied to the nonvolatile memory, the power supply indication signal generated by the detection circuit is in the first state, wherein when the detection circuit determines that the second power supply voltage is applied to the nonvolatile memory, the power supply voltage indication signal generated by the detection circuit is in the second state.

10. The nonvolatile memory of claim 7, further comprising a configuration memory coupled to the configuration circuit for storing configuration information to configure the configuration circuit to operate with respect to the power supply voltage indication signal, wherein the configuration memory can be in a first configuration state, a second configuration state, and a third configuration state, wherein when the configuration memory is in the first configuration state, the configuration circuit configures the control circuitry to operate in accordance with the power supply voltage indication signal, wherein when the configuration memory is in the second configuration state, the configuration circuit configures the control circuitry to operate at the first power supply voltage regardless of the power supply voltage indication signal, wherein when the configuration memory is in the third configuration state, the configuration circuit configures the control circuitry to operate at the second power supply voltage regardless of the power supply voltage indication signal.

11. The nonvolatile memory of claim 7, wherein the first power supply voltage is approximately 5 volts and the second power supply voltage is approximately 3.3 volts.

12. The nonvolatile memory of claim 7, wherein the nonvolatile memory includes memory cells that are electrically programmable and erasable.

13. The nonvolatile memory of claim 7, wherein the control circuitry can operate at a plurality of power supply voltages, including the first and second power supply voltages, wherein the configuration circuit can configure the control circuitry to operate at one of the plurality of power supply voltages at one time.

14. A method for automatically configuring a nonvolatile memory with respect to the voltage level of a power supply applied to the nonvolatile memory in accordance with a power supply voltage indication signal, wherein the power supply can be in either a first voltage level or a second voltage level, wherein the method comprises the steps of:

(a) receiving the power supply voltage indication signal in a configuration circuit, wherein the power supply voltage indication signal indicates the voltage level of the power supply applied to the nonvolatile memory, wherein the power supply voltage indication signal is in a first state when the power supply has the first voltage level and is in a second state when the power supply has the second voltage level;

(b) configuring the nonvolatile memory by the configuration circuit in accordance with the power supply voltage indication signal to operate at one of the first and second voltage levels of the power supply applied to the control circuitry, wherein when the power supply voltage indication signal is in the first state, then

(i) causing each of a plurality of input buffers of the control circuitry to have a first device size ratio for a trip point that is associated with the first voltage level of the power supply;

(ii) causing an output compensation circuit in each of a plurality of output buffers of the control circuitry to be disabled;

(iii) causing a boost circuit of the control circuitry to boost the first voltage level of the power supply applied to a selected word line of the memory array during a read operation to the second voltage level;

(iv) causing a memory operation control engine of the control circuitry to select a first memory operation control algorithm associated with the first voltage level of the power supply;

wherein when the power supply voltage indication signal is in the second state, then

(v) causing each of the plurality of input buffers of the control circuitry to have a second device size ratio for the trip point that is associated with the second voltage level of the power supply;

(vi) causing the output compensation circuit in each of the plurality of output buffers of the control circuitry to be enabled;

(vii) causing the boost circuit of the control circuitry to be disabled;

(viii) causing the memory operation control engine of the control circuitry to select a second memory operation control algorithm associated with the second voltage level of the power supply.

15. The method of claim 14, further comprising the steps of:

(A) detecting the voltage level of the power supply applied to the nonvolatile memory;

(B) generating the power supply voltage indication signal in accordance with the voltage level detected, wherein when the power supply is detected to have the first voltage level, the power supply voltage indication signal generated is in the first state, wherein when the power supply is detected to have the second voltage level, the power supply voltage indication signal generated is in the second state.

16. The method of claim 14, wherein the configuration circuit receives the power supply voltage indication signal from an external circuit via an input pin of the nonvolatile memory.

17. The method of claim 14, wherein the nonvolatile memory includes memory cells that are electrically programmable and erasable.

18. The method of claim 14, wherein the first voltage level is approximately 5 volts and the second voltage level is approximately 3.3 volts.