Internal bus for work station interfacing means
First Claim
Patent Images
1. A work station, including a central processing unit (CPU), said work station comprising:
- a first integrated circuit interface block connected to a first external bus;
a second integrated circuit interface block connected to a first memory;
a third integrated circuit interface block connected to a peripheral unit; and
a local bus connected to said CPU and first, second and third blocks;
wherein each block includes operating units disposed therein and an internal bus interconnecting said operating units; and
wherein each interface block is adapted to operate at the same clock frequency as said CPU, but with operational signals generated on its respective internal bus independently of said CPU.
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Abstract
A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips connected to an external bus, memory and peripheral unit, respectively, and a local bus connected to the CPU and interface chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each interface chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU.
36 Citations
13 Claims
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1. A work station, including a central processing unit (CPU), said work station comprising:
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a first integrated circuit interface block connected to a first external bus; a second integrated circuit interface block connected to a first memory; a third integrated circuit interface block connected to a peripheral unit; and a local bus connected to said CPU and first, second and third blocks; wherein each block includes operating units disposed therein and an internal bus interconnecting said operating units; and wherein each interface block is adapted to operate at the same clock frequency as said CPU, but with operational signals generated on its respective internal bus independently of said CPU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12)
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11. An integrated circuit interface block, connected to central processing unit (CPU) by a local bus, comprising:
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a plurality of operating units; and an internal bus interconnecting said operating units, said interface block being adapted to operate at the same clock frequency as said CPU, but with operational signals generated on said internal bus independently of said CPU; wherein said internal bus includes data signal lines, address signal lines, operational unit identification lines, command signal lines and an internal arbiter; wherein said operating units are assigned respective different priorities; and wherein each operating unit is adapted to transmit a bus request signal and a unit identification signal to said internal arbiter which in response is adapted to transmit a bus grant signal granting access to the internal bus to the requesting operating unit having the highest priority. - View Dependent Claims (13)
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Specification