Internal bus for work station interfacing means

• US 5,363,492 A
• Filed: 08/30/1991
• Issued: 11/08/1994
• Est. Priority Date: 08/31/1990
• Status: Expired due to Term

• Current Assignee: Transpacific Digital Systems LLC (Intellectual Ventures LLC)
• Original Assignee: NCR Corporation
• Inventors: King, Edward C., Goeppel, Anton
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Hafiz, Tariq R.
• Application Number:
  US07/752,371
• Time in Patent Office: 1,166 Days
• Field of Search: 395/325, 395/250, 395/425, 395/725, 395/800, 395/425, 395/775, 395/806, 364/200, 370/85.6, 770/85.6
• US Class Current: 710/306
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips connected to an external bus, memory and peripheral unit, respectively, and a local bus connected to the CPU and interface chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each interface chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU.

Claims

1. A work station, including a central processing unit (CPU), said work station comprising:

a first integrated circuit interface block connected to a first external bus;

a second integrated circuit interface block connected to a first memory;

a third integrated circuit interface block connected to a peripheral unit; and

a local bus connected to said CPU and first, second and third blocks;

wherein each block includes operating units disposed therein and an internal bus interconnecting said operating units; and

wherein each interface block is adapted to operate at the same clock frequency as said CPU, but with operational signals generated on its respective internal bus independently of said CPU.

2. A work station according to claim 1 wherein said external bus is adapted to transfer information at a frequency which differs from the operating frequency of said CPU.

3. A work station according to claim 1, further comprising:

a fourth interface block connected to a second external bus.

4. A work station according to claim 1, further comprising:

a fifth interface block connected to a second memory.

5. A work station according to claim 1 wherein each internal bus includes data signal lines, address signal lines, operational unit identification lines and command signal lines.

6. A work station according to claim 5 wherein said local bus includes data signal lines, address signal lines, control signal lines and a clock signal line.

7. A work station according to claim 1, wherein:

said first interface block includes an internal arbiter;

the operating units of said first interface block are assigned respective different priorities; and

each operating unit of said first interface block is adapted to transmit a bus request signal and a unit identification signal to said internal arbiter which in response is adapted to transmit a bus grant signal granting access to the internal bus (first internal bus) of said first interface block to the requesting operating unit having the highest priority.

8. A work station according to claim 7, wherein said first internal bus includes a burst mode control line for each of the associated operating units, whereby a first operating unit obtaining access to said first internal bus and activating its burst mode control line is effective to lock said first internal bus for a plurality of operating cycles on said first internal bus, during which data is transferred continuously in a burst mode.

9. A work station according to claim 8, wherein said first internal bus includes a busy mode control line for each of the associated operating units, activation of a busy mode control line indicating that the associated operating unit is busy.

10. A work station according to claim 8, wherein said first internal bus includes a retry signal line for each of the associated operating units which attempts to obtain access to another of said operating units which is currently busy, an active retry signal being effective to enable said internal arbiter to reorder the priority on said internal bus.

12. A work station according to claim 1 wherein said first integrated circuit interface block is a integrated circuit chip, said second integrated circuit interface block is a integrated circuit chip, and said third integrated circuit interface block is a integrated circuit chip.

11. An integrated circuit interface block, connected to central processing unit (CPU) by a local bus, comprising:

a plurality of operating units; and

an internal bus interconnecting said operating units, said interface block being adapted to operate at the same clock frequency as said CPU, but with operational signals generated on said internal bus independently of said CPU;

wherein said internal bus includes data signal lines, address signal lines, operational unit identification lines, command signal lines and an internal arbiter;

wherein said operating units are assigned respective different priorities; and

wherein each operating unit is adapted to transmit a bus request signal and a unit identification signal to said internal arbiter which in response is adapted to transmit a bus grant signal granting access to the internal bus to the requesting operating unit having the highest priority.

13. A work station according to claim 11 wherein said integrated circuit interface block is a integrated circuit chip.