System for improving access time to video display data using shadow memory sized differently from a display memory

• US 5,363,500 A
• Filed: 01/24/1991
• Issued: 11/08/1994
• Est. Priority Date: 01/25/1990
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Takeda, Koji
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/645,902
• Time in Patent Office: 1,384 Days
• Field of Search: 395/425, 395/164, 395/166, 395/115, 395/400, 340/750, 340/799, 345/185, 345/201
• US Class Current: 345/535
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A system for improving access time to video display data uses a shadow memory having fewer storage locations than a display memory. The shadow memory and the display memory share a set of addresses such that data written to the display memory, at an address shared by the shadow memory, is identically written to the shadow memory. Read requests directed to the display memory result in: (a) data returned from the shadow memory when access to a shared address is requested, and (b) data returned from the display memory when access to a non-shared address is requested.

Claims

1. An information processing device (IPD), comprising:

a) a central processing unit (CPU) coupled to a data bus;

b) a display memory having a first size corresponding to a first address space;

c) a video controller;

d) a shadow memory, coupled to said data bus having a second size corresponding to a second address space, the first size being later than the second size;

e) arbitration means, coupled to said CPU, said data bus, said display memory and said video controller, for arbitrating between access requests from said CPU and said video controller, such that when said CPU requests write access to said display memory, said CPU is forced to wait until said arbitration means permits said CPU to access said display memory;

wherein said CPU concurrently writes identical data into said display memory and into said secondary memory when the second address space overlaps with the first address space; and

selecting means

(1) for selecting said shadow memory in response to a reading request by said CPU when second address space overlaps with the first address space, and

(2) for selecting said display memory when the data is written exclusively in said display memory in response to a read request by said CPU.