Nitride cap sidewall oxide protection from BOE etch

• US 5,364,804 A
• Filed: 11/03/1993
• Issued: 11/15/1994
• Est. Priority Date: 11/03/1993
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ho, Yen-Shyh, Chen, Chien-Yung
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/145,160
• Time in Patent Office: 377 Days
• Field of Search: 437/40, 437/41, 437/44, 437/195, 437/978, 437/984, 437/52, 437/24, 437/241
• US Class Current: 438/592
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: Y10S 438/911 Differential oxidation and etching
• CPC Class Codes: Y10S 438/918 Special or nonstandard dopant
• CPC Class Codes: Y10S 438/966 Selective oxidation of ion-amorphousized layer

Abstract

A method of forming a self-aligned contact is disclosed. A pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a TEOS layer over said silicon nitride layer is provided on a silicon substrate. Each of the layers has its sides open to the ambient. Inert ions are implanted into the substrate which is not covered by the polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of the substrate. The pattern of polysilicon gate electrode stack and the surface of the said substrate are subjected to a thermal oxidizing ambient which causes oxidation of the sides open to the ambient of the polysilicon layer to form a second polyoxide layer on the sides of the polysilicon layer. A second silicon nitride layer is formed over the pattern of stack and the surface of the substrate. The second silicon nitride layer is anisotropically etched to remove the second silicon nitride from the top of the stack and from over the surface of the substrate while leaving the second silicon nitride layer remaining upon the sides of the stack to form a self-aligned opening to regions within the silicon substrate. A self-aligning contact to the regions is formed through said opening.

Claims

1. The method of forming a self-aligned contact to regions within a silicon substrate without lithography comprising:

providing a pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a silicon oxide layer over said silicon nitride layer, wherein each of said layers has its sides open to the ambient;

implanting inert ions into said substrate which is not covered by said polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of said substrate;

subjecting the said pattern of polysilicon gate electrode stack and said surface of said substrate to a thermal oxidizing ambient which causes oxidation of the said sides open to the ambient of said polysilicon layer to form a second polyoxide layer on the sides of said polysilicon layer;

forming a second silicon nitride layer over said pattern of stack and said surface of said substrate;

anisotropically etching said second silicon nitride layer to remove said second silicon nitride from the top of said stack and from over said surface of said substrate while leaving said second silicon nitride layer remaining upon said sides of said stack to form a self-aligned opening to regions within said silicon substrate; and

forming said self-aligning contact to said regions through said opening.

2. The method of claim 1 wherein said silicon oxide layer overlying said silicon nitride layer is composed of tetraethoxysilane (TEOS) deposited to a thickness of between about 300 to 500 Angstroms and wherein said TEOS layer protects said underlying silicon nitride layer from damage during said subsequent etching process.

3. The method of claim 1 wherein said inert ions are N₂ ions implanted at a dosage of between about 3 E 15 to 4 E 15 atoms/cm² at an energy of between about 50 to 60 KeV.

4. The method of claim 1 wherein said thermal oxidizing ambient is at a temperature of between about 900°

and 1000°

C. and said second polyoxide layer is formed to a thickness of between about 1850 to 2350 Angstroms.

5. The method of claim 1 wherein said second silicon nitride layer is deposited to a thickness of between about 550 to 650 Angstroms.

6. The method of claim 1 wherein said etching of said second silicon nitride layer is performed by a reactive ion etch and wherein the selectivity of said etching process is about 1:

3 (silicon oxide;

silicon nitride).

7. The method of forming a self-aligned contact to regions within a silicon substrate without lithography comprising:

providing a silicon oxide gate dielectric over the surface of said silicon substrate;

depositing a layer of polysilicon to form a gate electrode over the surface of said silicon oxide gate dielectric;

growing a first thermal polyoxide layer over the top of said polysilicon gate electrode layer;

depositing a first silicon nitride layer over said first thermal polyoxide layer;

depositing a silicon oxide layer over said first silicon nitride layer;

etching said silicon oxide, silicon nitride, polyoxide, polysilicon, and gate dielectric layers to form a pattern of polysilicon gate electrode stacks on the surface of said substrate wherein each of said layers has its sides open to the ambient;

implanting inert ions into said substrate which is not covered by said polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of said substrate;

subjecting the said pattern of polysilicon gate electrode stack and said surface of said substrate to a thermal oxidizing ambient which causes oxidation of the said sides open to the ambient of said polysilicon layer to form a second polyoxide layer on the sides of said polysilicon layer;

forming a second silicon nitride layer over said pattern of stack and said surface of said substrate;

anisotropically etching said second silicon nitride layer to remove said second silicon nitride from the top of said stack and from over said surface of said substrate while leaving said second silicon nitride layer remaining upon said sides of said stack to form a self-aligned opening to regions within said silicon substrate; and

forming said self-aligning contact to said regions through said opening

8. The method of claim 7 wherein said silicon oxide layer overlying said silicon nitride layer is composed of tetraethoxysilane (TEOS) deposited to a thickness of between about 300 to 500 Angstroms and wherein said TEOS layer protects said underlying silicon nitride layer from damage during said subsequent etching process.

9. The method of claim 7 wherein said inert ions are N₂ ions implanted at a dosage of between about 3 E 15 to 4 E 15 atoms/cm² at an energy of between about 50 to 60 KeV.

10. The method of claim 7 wherein said thermal oxidizing ambient is at a temperature of between about 900°

and 1000°

C. and wherein said second polyoxide layer is formed to a thickness of between about 1850 to 2350 Angstroms.

11. The method of claim 7 wherein said second silicon nitride layer is deposited to a thickness of between about 550 to 650 Angstroms.

12. The method of claim 7 wherein said etching of said second silicon nitride layer is performed by a reactive ion etch and wherein the selectivity of said etching process is about 1:

3 (silicon oxide;

silicon nitride).