CMOS voltage controlled ring oscillator

• US 5,365,204 A
• Filed: 10/29/1993
• Issued: 11/15/1994
• Est. Priority Date: 10/29/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ghose, Arun K., Meltzer, David, Wang, Wen-Yuan, Wu, Leon L., Konian, Richard R., Angiulli, John M., Levine, Samuel R.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/145,364
• Time in Patent Office: 382 Days
• Field of Search: 331/57, 331/135, 331/177 R, 331/179
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit'"'"'s oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.

Claims

1. A variable frequency digital oscillator comprising:

a digital ring oscillator circuit having two supply voltages Vss and Vdd; and

an odd number of CMOS inverters connected in cascade to form a loop; and

a plurality of CMOS transmission gates coupled between each adjacent pair of said CMOS inverters; and

a MOS capacitor connected between the output of each transmission gate and said Vss supply.

2. An oscillator according to claim 1 wherein the CMOS transmission gates are formed of PMOS and NMOS transistors and having DC gate voltages of the CMOS transmission gates PMOS and NMOS transistors which are different and each different DC voltage is between Vss and Vdd.

3. An oscillator according to claim 2 wherein each transmission gate and a MOS capacitor form an RC delay element having a delay proportional to the gate voltages on the transmission gate PMOS and NMOS transistor gates, and wherein a variation of said DC gate voltages changes the frequency of oscillation of the ring oscillator circuit.

4. An oscillator according to claim 3 wherein is provided an odd number of inverters coupled in cascade with a CMOS RC delay element having a delay proportional to the gate voltages on the transmission gate PMOS and NMOS transistor gates coupled between two adjacent ones of said odd number of inverters, and having transmission gates connected to bypass an even number of inverters of said ring oscillator circuit;

and wherein the output of the last unbypassed inverter is connected to the input of the first of said odd number of CMOS inverters to form a ring loop.

5. An oscillator according to claim 4 wherein in operation said bypass transmission gates change the frequency of oscillation of the circuit.

6. An oscillator according to claim 3 wherein is provided an even multiple number of inverters coupled in cascade with a CMOS RC delay element having a delay proportional to the gate voltages on the transmission gate PMOS and NMOS transistor gates coupled between two adjacent ones of said even number of multiple inverters, and having a plurality of said ring oscillator circuits connected in cascade;

and wherein transmission gate PMOS and NMOS transistor gates are connected to bypass individual circuits, and the output of the last unbypassed inverter is connected to the input of an inverter, not one of said even multiple number of inverters, whose output is connected to the first of the plurality of circuits to form a loop.

7. An oscillator according to claim 6 wherein operation of said bypass transmission gates changes the frequency of oscillation of the circuit.

8. An oscillator according to claim 7 wherein is also provided an odd multiple number of inverters coupled in cascade with a CMOS RC delay element having a delay proportional to the gate voltages on the transmission gate PMOS and NMOS transistor gates coupled between two adjacent ones of said odd number of multiple inverters, and having transmission gates connected to bypass an even number of inverters of said ring oscillator circuits;

and wherein the output of the last unbypassed inverter is connected to the input of the first of said odd number of CMOS inverters to form a ring loop, and the combined plurality of inverters widens the range of possible oscillation frequencies of the oscillator circuit.

9. An oscillator according to claim 1 wherein said Vss power supply is ground.