Precision time measurements

• US 5,365,238 A
• Filed: 11/29/1993
• Issued: 11/15/1994
• Est. Priority Date: 11/29/1993
• Status: Expired due to Term

• Current Assignee: Wide Bank Systems, Inc.
• Original Assignee: Wide Band Systems, Inc.
• Inventors: Sullivan, William B.
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US08/158,947
• Time in Patent Office: 351 Days
• Field of Search: 342/195, 342/147, 342/175, 342/194, 342/56
• US Class Current: 342/195
• CPC Class Codes: G01R 29/02 Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means

Abstract

A circuit arrangement that utilizes digital data representative of the amplitude of an RF pulse envelope is disclosed. The circuit arrangement comprises a PROM having prestored and addressable routines and a nine stage sequentially arranged eight (8) bit latches that are clocked at a rate of 25 nanoseconds. The circuit arrangement determines, within 25 nanoseconds, when the maximum value of the RF pulse envelope is within a selectable 6 dB or 3 dB point and generates a control signal SV that causes the data in the upper stages of the nine stage latches to be frozen and further generates an address that is routed to the PROM, wherein a family of waveform shapes are accessed. The circuit arrangement provides for four (4) data points that are examined by prestored routines of the PROM and compared against the prestored family of waveform shapes, and, upon a match therebetween, determines the time of arrival (TOA) and pulse width of the RF pulse envelope being received by the circuit arrangement.

Claims

1. A circuit arrangement for receiving, holding and measuring an RF pulse envelope having an amplitude with predetermined rise and fall times and comprising digital words having a predetermined number of bits with a predetermined bit resolution, said circuit arrangement comprising:

(a) a first plurality of sequential latches responsive to a timing signal having a predetermined frequency and each latch receiving and storing one of said digital words, said first plurality of latches each having an output and arranged into lower and upper stages with one of the said lower stages serving as a reference stage;

(b) a summing reference network having an output and first and second inputs with the first input being connected to said output of said reference stage and the second input being connected to a reference quantity comprising a digital word and defining a predetermined reference point of the RF pulse envelope;

(c) a first plurality of subtracting networks each having an output and first and second inputs, said plurality of subtracting networks being arranged so that one of each has its first input respectively connected to the output of said lower and upper stages, except for said reference stage, of said first plurality of latches, each of said first plurality of substituting networks having its second input connected to said output of said summing reference network;

(d) a logic element having inputs connected to each of said outputs of said first plurality of subtracting networks anti generating an output control signal SV in the absence of all signals on its inputs, the occurrence of said output control signal SV being indicative that the sum of both the contents of said reference stage and the contents of said reference quantity is within said predetermined point of the maximum amplitude of the RF pulse envelope;

(e) a second plurality of sequential latches each having input and output stages, an output and first and second inputs and all being responsive to said control signal SV and said timing signal, said second plurality of latches being arranged in parallel with and receiving and storing the digital words received and stored by said upper stages of said first plurality of latches;

(f) a second plurality of subtracting networks each having an output and first and second inputs, a first network of which has its input connected to the output of the first latch of said second plurality of latches and its second input connected to the output of the second latch of said second plurality of latches, a second network of which has its first input connected to the second input of the first network and its second input connected to the output of the third latch of said second plurality of latches, and a third network of which has its first input connected to the second input of said second network and its second input connected to the output of the fourth latch of said second plurality of latches; and

(g) a PROM having prestored and addressable routines and receiving the outputs of said second plurality of subtracting networks, the outputs of said first sequential latches and the output signal SV, said output of the reference stage containing first data which is in coincidence with said control signal SV and which defines the amplitude of the RF pulse envelope at said predetermined point, said output of said lower latches of said first plurality of latches containing second data that defines the preceding and subsequent amplitudes of the RF pulse envelope relative to said predetermined point, said output of said second plurality of subtracting networks defining an address to access a family of waveform shapes having a peak value defined by said predetermined point, said PROM further having routines so that said preceding and subsequent amplitudes of the RF pulse envelope are compared against each of the family of waveform shapes to define a match that provides the time location, relative to the occurrence of said control signal SV, of the 3 dB point on the RF pulse envelope, said time location corresponding to a time of arrival (TOA) parameter of said RF pulse envelope and also defining the pulse width of said RF pulse envelope, said time location being definable within selectable increments of said predetermined frequency of said timing signal.

2. The circuit arrangement according to claim 1, wherein said RF pulse envelope has a rise time which exceeds 6 dB in a 75 nanosecond duration and a fall time which exceeds 6 dB within a duration of 125 nanoseconds.

3. The circuit arrangement according to claim 1, wherein each of said digital words comprising said RF pulse envelope has eight (8) bits with each bit having a resolution of 0.5 dB.

4. The circuit arrangement according to claim 1, wherein said timing signal has a repetition rate of 25 nanoseconds.

5. The circuit arrangement according to claim 1, wherein said first and second plurality of latches contain eight (8) bits of information each representative of a particular magnitude of the amplitude of said RF pulse envelope.

6. The circuit arrangement according to claim 1, wherein the first plurality of sequential latches are arranged so that their lower stages comprises first, second, third and fifth sequential latches, said reference stage comprises a fourth sequential latch, and said upper stage comprises sixth, seventh, eighth and ninth sequential latches.

7. The circuit arrangement according to claim 5, wherein said summing reference network receives an eight (8) bit quantity on both its first and second inputs and said reference quantity is also an eight (8) bit quantity having a bit weight of 0.5 dB and representing one of the -3 dB and -6 dB reference points of said RF pulse envelope.

8. The circuit arrangement according to claim 5, wherein each of said first plurality of subtracting networks receives an eight (8) bit quantity on both its first and second inputs and provides a one (1) bit quantity on its output when said first input exceeds said second input.

9. The circuit arrangement according to claim 5, wherein each of said first and second inputs of each of said second plurality of subtracting networks receives an eight (8) bit quantity and supplies a four (4) bit quantity representative of the difference of the quantities of its first and second inputs, said second plurality of subtracting networks having each of its third, second and first networks supplying a four (4) bit quantity that is arranged into a composite twelve (12) bit address that is used for addressing said addressable routines of said PROM.

10. The circuit arrangement according to claim 1, wherein said second data defining said precedent amplitude data comprise a first sample of amplitude occurring 25 nanoseconds before said occurrence of said control signal SV and said subsequent amplitude data comprises second, third and fourth samples of amplitude data occurring within 75 nanoseconds after said occurrence of said control signal SV.

11. The circuit arrangement according to claim 10, wherein said first, second, third and fourth samples each represents a particular magnitude and are curve fitted by a routine selected from the group comprising a third or higher order polynominal expressions some of which include natural exponents and all of which provide a curve which passes through all of said data represented by said first, second, third and fourth samples.

12. The circuit arrangement according to claim 7, wherein said time location is defined by an eight (8) bit word and each of said increments corresponds to 0.39 nanoseconds.

13. The circuit arrangement according to claim 1, wherein said reference quantity corresponds to a 6 dB reference point.

14. The circuit arrangement according to claim 1, wherein said reference quantity corresponds to a 3 dB reference point.

15. A method for measuring an RF pulse envelope having an amplitude with definable rise and fall times and comprising digital words having a predetermined number of bits with a predetermined bit resolution, said method comprising the steps of:

(a) providing a first plurality of sequential latches responsive to a timing signal having a predetermined frequency and each latch receiving and storing one of said digital words, said first plurality of latches each having an input and output and arranged into lower and upper stages with one of said lower stages serving as a reference stage;

(b) providing a summing reference network having an output and first and second inputs with the first input connected to said output of said reference stage;

(c) providing a reference quantity comprising a digital word which defines a predetermined point of said RF pulse envelope;

(d) selecting said predetermined point to correspond to the -6 dB point of said RF pulse envelope and connecting said reference quantity to said second input of said summing reference network;

(e) providing a first plurality of subtracting networks each having an output and first and second inputs, said plurality of subtracting networks being arranged so that each one has its first input respectively connected to the output of said lower and upper stages, except for said reference stage, of said first plurality of latches, each of said first plurality of subtracting networks having its second input connected to said output of said summing reference network;

(f) a logic element having inputs connected to each of said outputs of said first plurality of subtracting networks and generating an output control signal SV in the absence of any signal on its inputs, the occurrence of said output control signal SV being indicative that the sum of both the contents of said reference stage and the contents of said reference quantity is within the -6 dB point of the maximum amplitude of the RF pulse envelope;

(g) providing a second plurality of sequential latches each having input and output stages, an output and first and second inputs and all being responsive to said control signal SV and to said timing signal, said second plurality of latches being arranged in parallel with and receiving and storing the digital words received and stored by said upper stages of said first plurality of latches;

(h) providing a second plurality of subtracting networks each having an output and first and second inputs, a first network which has its first input connected to the output of the first latch of said second plurality of latches and its second input connected to the output of the second latch of said second plurality of latches, a second network which has its first input connected to the second output of said first network and a second input connected to the output of the third latch of said second plurality of latches, and a third network which has its first input connected to the second input of said second network and its second input connected to the output of the fourth latch of said second plurality of latches; and

(i) providing a PROM having prestored and addressable routines and receiving the outputs of said second plurality of subtracting networks, the outputs of said first sequential latches and the output signal SV, said output of the reference stage containing first data which is in coincidence with said control signal SV and which defines the amplitude of the RF pulse at said predetermined -6 dB point, said output of said lower latches of said first plurality of latches comprising second data that defines the precedent and subsequent amplitudes of the RF pulse envelope relative to said predetermined -6 dB point, said output of said plurality of networks defining an address to access a family of waveform shapes having a peak value as defined by said -6 dB predetermined point, said PROM having further routines so that said precedent and subsequent amplitudes of the RF pulse envelope are compared against each of the family of waveform shapes to define a match therebetween that provides the time location, relative to the occurrence of said control signal SV, of the -3 dB point on the RF pulse envelope, said time location corresponding to a time of arrival (TOA) parameter of said RF pulse envelope and also defining the pulse width of said RF pulse envelope, said time location being definable within selectable increments of said predetermined frequency of said timing signal.

16. The method according to claim 15, wherein said RF pulse envelope has a rise time which exceeds 6 db in a 75 nanosecond duration and a fall time which exceeds 6 db within a duration of 125 nanoseconds.

17. The method according to claim 15, wherein each of said digital words comprising said RF pulse envelope includes eight (8) bits with each bit having a resolution of 0.5 dB.

18. The method according to claim 15, wherein said timing signal has a repetition rate of 25 nanoseconds.

19. The method according to claim 15, wherein said first and second plurality of latches contain eight (8) bits of information representative of a respective digital word comprising said RF pulse envelope.

20. The method according to claim 15, wherein the first plurality of sequential latches are arranged so that their lower stages comprises first, second, third and fifth sequential latches, said reference stage comprises a fourth sequential latch, and said upper stage comprises sixth, seventh, eighth and ninth sequential latches.

21. The method according to claim 15, wherein said summing reference network receives an eight (8) bit quantity on both its first and second inputs and said reference quantity is also an eight (8) bit word having a bit weight of 0.5 dB and representing one of the -3 dB and -6 dB reference points of said RF pulse envelope.

22. The method according to claim 19, wherein each of said first and second inputs of each of said second plurality of subtracting networks receives an eight (8) bit quantity and supplies a four (4) bit quantity representative of the difference of the quantities of its first and second inputs, said second plurality of subtracting networks having each of its third, second and first networks supplying a four (4) bit quantity that is arranged into a composite twelve (12) bit address that is used for addressing said addressable routines of said PROM.

23. The method according to claim 15, wherein said second data defining said precedent amplitude comprises a first sample of amplitude data occurring 25 nanoseconds before said occurrence of said control signal SV and said subsequent amplitude data comprises second, third and fourth samples of amplitude data occurring within 75 nanoseconds after said occurrence of said control signal SV.

24. The method according to claim 23, wherein said first, second, third and fourth samples each represent a magnitude and are curve fitted by a routine selected from the group comprising a third or higher polynominal expressions some of which include natural exponents and all of which provide a curve which passes through all of said data represented by said first, second, third and fourth samples.

25. The method according to claim 15, wherein said time location is defined by an eight (8) bit word and each of said increments corresponds to 0.39 nanoseconds.