High speed recorded information duplicating equipment

• US 5,365,381 A
• Filed: 06/03/1991
• Issued: 11/15/1994
• Est. Priority Date: 01/06/1987
• Status: Expired due to Term

• Current Assignee: Broadbus Technologies, Inc. (Lenovo Group Ltd.)
• Original Assignee: Magic Music Cassette Company
• Inventors: Scheffler, Robert G.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/709,714
• Time in Patent Office: 1,261 Days
• Field of Search: 360/13, 360/15, 360/16, 360/17, 360/32, 360/39, 369/8, 369/84, 369/85
• US Class Current: 360/15
• CPC Class Codes: G11B 2220/20 Disc-shaped record carriers
• CPC Class Codes: G11B 2220/2545 CDs
• CPC Class Codes: G11B 2220/41 Flat as opposed to hierarchical combination, e.g. library of tapes or discs, CD changer, or groups of record carriers that together store one title
• CPC Class Codes: G11B 2220/61 wherein solid state memory is used for storing A/V content storing computer data in solid state memories G06F
• CPC Class Codes: G11B 2220/90 Tape-like record carriers
• CPC Class Codes: G11B 2220/913 Digital audio tape [DAT] format
• CPC Class Codes: G11B 27/002 Programmed access in sequence to a plurality of record carriers or indexed parts, e.g. tracks, thereof, e.g. for editing; transfer of record carriers from magazine G11B15/68, G11B17/10; G11B17/22
• CPC Class Codes: G11B 27/005 Reproducing at a different information rate from the information rate of recording for television signals H04N5/783
• CPC Class Codes: G11B 27/02 Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
• CPC Class Codes: G11B 27/024 on tapes G11B27/028, G11B27/029 take precedence
• CPC Class Codes: G11B 27/028 with computer assistance
• CPC Class Codes: G11B 27/031 Electronic editing of digitised analogue information signals, e.g. audio or video signals
• CPC Class Codes: G11B 5/86 Re-recording, i.e. transcribing information from one magnetisable record carrier on to one or more similar or dissimilar record carriers by varying the order of the information G11B27/029, G11B27/036

Abstract

A customized album recording system is under the control of a central microprocessor or mini-computer. A master library or storage medium is filled with a repertoire of recorded information items (such as musical selections) which may originate with any suitable source, such as phonograph records, tapes, sound tracks, compact discs, or the like. Each information item is stored in the library under its own address. On read out, an operator keys in the addresses identifying the selected items which are read out of the library medium and stored in a large capacity memory, usually to provide about forty-five minutes of total listening time. Then, all of the music is read out of that large capacity memory and recorded at a high speed onto a suitable album size medium, such as a tape cassette, for example. The source music and the customized album music are usually recorded in an analog form. The music which is processed within the system is in a digital form. Thus, the various transfers of music from the master storage to the recorded album, may be accomplished at a high speed of digital transmission. In an alternative embodiment, instead of reading out an entire album amount of recorded information items, the central computer successively reads out limited amounts of data on a demand and fetch basis. A computer provides both the analog-to-digital and the digital-to-analog conversions in order to improve fidelity.

Claims

1. A system for duplicating selected prerecorded items of information, the items of information being prerecorded on a source medium, the system duplicating the items of information onto a destination medium as a custom album, the system comprising

means for generating first digital signals corresponding to selected items of information on the source medium;

means for storing said first digital signals in a master storage library under item addresses which individually identify each of the selected items of information;

means for retrieving the first digital signals from the master storage library and for generating second digital signals corresponding to a plurality of the selected items of information;

buffer storage means for receiving and storing said second digital signals and for generating third digital signals;

destination control means for controlling said buffer storage means and for controlling the recording of the items of information on to the destination medium;

said destination control means further including

control processor for identifying the information in said buffer storage means;

memory address generator operatively connected to the control processor for generating address signals to access information in the buffer storage means;

bus control means operatively connected to said buffer storage means by a first bus for controlling the generation of said third digital output signals of said buffer storage means;

request control logic means operatively connected to said bus control means for controlling said bus control means;

byte unstacker means operatively connected to said buffer storage means for receiving and unstacking the third digital output signals of the buffer storage means; and

first-in-first-out (FIFO) buffer means operatively connected to said byte unstacker means for receiving the unstacked third digital output signals and for generating fourth signals.

2. The system of claim 1 wherein said prerecorded items each include at least two tracks which have a predetermined relationship to each other,

said FIFO buffer means having a FIFO buffer for each of said tracks, p1 said FIFO buffers simultaneously and separately generating said fourth signals for each of said tracks in said predetermined relationship,

said request control logic means causing said buffer storage means to generate output signals to said FIFO buffers sufficient to maintain said continuous output of said fourth signals from said FIFO buffers.

3. The system of claim 2 wherein said fourth signals are converted into analog signals, said system further including a digital to analog converter operatively connected to each of said FIFO buffers for converting said fourth signals from said FIFO buffers into said analog signals.

4. The system of claim 2 wherein said fourth signals are digital signals.

5. The system of claim 1 wherein said buffer storage means further includes

random access memory means for electronically storing and retrieving said recorded items of information,

data latch and driver means for enabling the retrieval of information from said random access memory means,

address decoding means for accessing said recorded items of information in said random access memory means, and

state control logic means for controlling said data latch and driver means and said random access memory means so that the desired data is retrieved from said random access memory means in the proper timing sequence.

6. A system for duplicating selected prerecorded items of information, the items of information being prerecorded on a source medium, the system duplicating the items of information onto a destination medium as a custom album, the system comprising

means for generating first digital signals corresponding to selected items of information on the source medium;

means for storing said first digital signals in a master storage library under item addresses which individually identify each of the selected items of information;

means for retrieving the first digital signals from the master storage library and for generating second digital signals corresponding to a plurality of the selected items of information;

buffer storage means for receiving and storing said second digital signals and for generating third digital signals;

destination control means for controlling said buffer storage means and for controlling the recording of the items of information on to the destination medium;

said means for generating said second digital signals further including

control processor for identifying the information in said buffer storage means;

memory address generator means responsive to said control processor for generating memory address signals corresponding to the selected items of information;

a first bus for transferring said memory address signals to said buffer storage means;

bus control means operatively connected to said buffer storage means by a second bus for controlling said buffer storage means;

first-in-first-out (FIFO) buffer means operatively connected to the output of said master storage library for sending said second digital signals, received from said master storage library, to a third bus;

byte stacker means operatively connected between said third bus and said buffer storage means for controlling said second digital signals between said FIFO and said buffer storage means; and

request control logic means operatively connected to said bus control means and said FIFO means, said request control means controlling said second digital signals so that said second digital signals are sent on to said third bus in a desired manner, and are stored in said buffer storage means at a desired memory address.

7. The system of claim 6 wherein said prerecorded items each include at least two tracks which have a predetermined relationship to each other,

said FIFO buffer means having a FIFO buffer for each of said tracks,

said FIFO buffers simultaneously and separately generating said second signals for each of said tracks in said predetermined relationship,

said request control logic means causing said buffer storage means to accept output signals from said FIFO buffers sufficient to maintain said continuous input of said second signals from said FIFO buffers.

8. The system of claim 6 further including an analog to digital converter for generating said first digital signals wherein said analog to digital converter converts a source of analog signals received from said source medium.

9. The system of claim 6 wherein said buffer storage means further includes

random access memory means for electronically storing and retrieving said recorded items of information,

data latch and driver means for enabling the storage of information into said random access memory means,

address encoding means for storing said recorded items of information in said random access memory means, and

state control logic means for controlling said data latch and driver means and said random access memory means so that the desired data is stored in said random access memory means in the proper timing sequence.

10. A system for duplicating selected prerecorded items of information, the items of information being prerecorded on a source medium, the system duplicating the items of information onto a destination medium as a custom album, the system comprising

means for generating first digital signals corresponding to selected items of information on the source medium;

means for storing said first digital signals in a master storage library under item addresses which individually identify each of the selected items of information;

means for retrieving the first digital signals from the master storage library and for generating second digital signals corresponding to a plurality of the selected items of information;

buffer storage means for receiving and storing said second digital signals and for generating third digital signals;

destination control means for controlling said buffer storage means and for controlling the recording of the items of information on to the destination medium;

said means for generating said second digital signals further including

control processsor for identifying the information in said buffer storage means;

memory address generator means responsive to said control processor for generating memory address signals corresponding to the selected items of information;

a first bus for transferring said memory address signals to said buffer storage means;

bus control means operatively connected to said buffer storage means by a second bus for controlling said buffer storage means;

first-in-first-out (FIFO) buffer means operatively connected to the output of said master storage library for sending said second digital signals, received from said master storage library, to a third bus;

byte stacker means operatively connected between said third bus and said buffer storage means for controlling said second digital signals between said FIFO and said buffer storage means;

request control logic means operatively connected to said bus control means and said FIFO means, said request control means controlling said second digital signals so that said second digital signals are sent on to said third bus in a desired manner, and are stored in said buffer storage means at a desired memory address;

said destination control means further including

control processor for identifying the information in said buffer storage means;

memory address generator operatively connected to the control processor for generating address signals to access information in the buffer storage means;

bus control means operatively connected to said buffer storage means by a first bus for controlling the generation of third said digital output signals of said buffer storage means;

request control logic means operatively connected to said bus control means for controlling said bus control means;

byte unstacker means operatively connected to said buffer storage means for receiving and unstacking the third digital output signals of the buffer storage means; and

first-in-first-out (FIFO) buffer means operatively connected to said byte unstacker means for receiving the unstacked third digital output signals and for generating fourth signals.

11. The system of claim 10 wherein said selected items each include at least two tracks which have a predetermined relationship to each other,

said FIFO buffer means having a FIFO buffer for each of said tracks,

said FIFO buffers simultaneously and separately generating said third signals for each of said tracks in said predetermined relationship,

said request control logic means causing said buffer storage means to generate output signals to said FIFO buffers sufficient to maintain said continuous output of said third signals from said FIFO buffers.

12. The system of claim 11 wherein said third signals are analog signals, said system further including a digital to analog converter operatively connected to each of said FIFO buffers for converting said third signals from said FIFO buffers into said analog signals.

13. The system of claim 11 wherein said third signals are digital signals.

14. The system of claim 10 wherein said buffer storage means further includes

random access memory means for electronically storing and retrieving said recorded items,

data latch and driver means for enabling the storage and retrieval of information in said random access memory means,

address encoding means for storing said recorded items information in said random access memory means,

address decoding means for accessing said recorded items of in said random access memory means, and

state control logic means for controlling said data latch and driver means and said random access memory means so that the desired data is stored in and retrieved from said random access memory means in the proper timing sequence.