Semiconductor memory device usable as static type memory and read-only memory and operating method therefor
First Claim
1. A semiconductor memory device, comprising:
- a first potential line for receiving a first potential;
a second potential line for receiving a second potential;
a third potential line for selectively receiving the first potential or the second potential;
a fourth potential line for selectively receiving the first potential or the second potential; and
at least one memory cell;
said memory cell including;
a first node and a second node provided with potentials which are complementary to each other;
first pull-up/pull-down means connected between either of said first and third potential lines and said first node;
second pull-up/pull-down means connected between either of said first and third potential lines and said second node,third pull-up/pull-down means connected between either of said second and fourth potential lines and said first node; and
fourth pull-up/pull-down means connected between either of said second and fourth potential lines and said second node.
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Accused Products
Abstract
Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.
A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.
40 Citations
27 Claims
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1. A semiconductor memory device, comprising:
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a first potential line for receiving a first potential; a second potential line for receiving a second potential; a third potential line for selectively receiving the first potential or the second potential; a fourth potential line for selectively receiving the first potential or the second potential; and
at least one memory cell;
said memory cell including;a first node and a second node provided with potentials which are complementary to each other; first pull-up/pull-down means connected between either of said first and third potential lines and said first node; second pull-up/pull-down means connected between either of said first and third potential lines and said second node, third pull-up/pull-down means connected between either of said second and fourth potential lines and said first node; and fourth pull-up/pull-down means connected between either of said second and fourth potential lines and said second node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit line pair each comprising a first bit line and a second bit line and arranged so as to cross said plurality of word lines; a first potential line for receiving a first potential; a second potential line for receiving a second potential; a third potential line for selectively receiving the first potential or the second potential; a fourth potential line for selectively receiving the first potential or the second potential; and a plurality of memory cells provided at the crossings of said plurality of word lines and plurality of bit line pairs each of said plurality of memory cells including; a first node and a second node provided with potentials which are complementary to each other; first pull-up/pull-down means connected between either of said first and third potential lines and said first node; second pull-up/pull-down means connected between either of said first and third potential lines and said second node; third pull-up/pull-down means connected between either of said second and fourth potential lines and said first node; and fourth pull-up/pull-down means connected to either of said second and fourth potential lines and said second node.
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18. A method of operating a semiconductor memory device comprising a first node and a second node provided with potentials (which are) complementary to each other, first pull-up/pull-down means connected between either of first and third potential lines and said first node, second pull-up/pull-down means connected between either of said first and third potential lines and said second node, third pull-up/pull-down means connected between either of the second and fourth potential lines and said first node, and fourth pull-up/pull-down means connected between either of said second and fourth potential lines and said second node,
said method comprising the steps of: -
providing a first potential to said first potential line; providing a second potential to said second potential line; selectively providing the first potential or the second potential to said third potential line; and selectively providing the first potential or the second potential to said fourth potential line.
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19. A semiconductor memory device comprising:
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at least one memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; and voltage applying means for selectively applying a voltage of either a high digital level or low digital level to each of said first and second terminals, whereby said memory cell may operate selectively as a SRAM cell, a ROM cell having a high digital level storage or as a ROM cell having a low digital level storage.
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20. A semiconductor memory device comprising:
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at least one memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; and voltage applying means for selectively applying a voltage of either a high digital level or a low digital level to each of said first and second terminals, whereby said memory cell may operate selectively as a SRAM cell, a ROM cell having a high digital level storage or as a ROM cell having a low digital level storage, wherein said voltage applying means comprises; a high voltage level reference source, a low voltage level reference source; and four conductive lines respectively connected to the first and second terminals of the two circuit portions, a first one of said conductive lines being supplied with said high voltage level reference source, a second one of said conductive lines being supplied with said low voltage level reference source, and the remaining conductive lines being independently selectively supplied with one of said high and low voltage level reference sources. - View Dependent Claims (21, 22, 23)
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24. A semiconductor memory device comprising:
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a plurality of memory cells arranged in an array of rows and columns, each memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; a plurality of parallel conductive lines extending along each column, the first and second terminals of said two circuit portions of each memory cell in each column connected to individual ones of said conductive lines corresponding thereto; and voltage applying means for selectively applying a voltage of either a high digital level or a low digital level to at least two of said conductive lines corresponding to each column, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.
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25. A semiconductor memory device comprising:
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a plurality of word lines and a plurality of bit lines crossing said plurality of word lines; a plurality of memory cells arranged in an array of rows and columns at crossing points of said plurality of word lines and said plurality of bit lines, each memory cell having switching transistors forming a latch circuit; a plurality of parallel conductive lines extending along each column, crossing said plurality of word lines, for selecting connection to the memory cells in the respective column; and voltage applying means for selectively applying a voltage of either high digital level or low digital level to at least two of said plurality of conductive lines corresponding to each columns, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.
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26. A semiconductor memory device comprising:
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a plurality of word lines and a plurality of bit lines crossing said plurality of word lines; a plurality of memory cells arranged in an array of rows and columns, each memory cell having an array of rows and columns, each memory cell having switching transistors forming a latch circuit; a plurality of parallel conductive lines arranged for every two columns, crossing said plurality of word lines, and for selective connection to the memory cells in the respective adjacent two columns; and voltage applying means for selectively applying a voltage of either high digital level or low digital level to at least two of said plurality of parallel conductive lines corresponding to each columns, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.
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27. A semiconductor memory device comprising:
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at least one memory cell, first line supplied with a voltage of low digital level, second line selectively supplied with one of voltages of high and low digital levels, third lines supplied with a voltage of high digital level, and fourth line selectively supplied with one of voltages of high and low digital levels, said memory cell comprising first and second storage nodes, a first MOS transistor connected between said first storage node and selected one of said first and second lines and having a gate electrode connected to said second storage node, a second MOS transistor connected between said second storage node and selected one of said first and second lines and having a gate electrode connected to said first storage node, a first element having a first node connected to selected one of said third and fourth lines and a second node connected to said first storage node, and a second element having a first node connected to selected one of said third and fourth lines and a second node connected to said second storage node.
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Specification