Semiconductor memory
First Claim
1. A semiconductor memory formed in a semiconductor integrated circuit comprising:
- a pair of data lines disposed substantially parallel and adjacent to each other;
a word line arranged so as to intersect with both data lines of said pair of data lines;
a dummy line arranged so as to intersect with both data lines of said pair of data lines;
a memory cell coupled to said word line and to at least one data line of said pair of data lines at a cross point of said word line and said at least one data line;
a dummy cell coupled to said dummy word line and to at least one data line of said pair of data lines at a cross point of said dummy word line and said at least one data line;
amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminal which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means;
precharging means for setting said pair of data lines at an intermediate potential between said first reference voltage and said second reference voltage; and
selecting means for selecting said word line and said dummy word line.
2 Assignments
0 Petitions
Accused Products
Abstract
A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
-
Citations
25 Claims
-
1. A semiconductor memory formed in a semiconductor integrated circuit comprising:
-
a pair of data lines disposed substantially parallel and adjacent to each other; a word line arranged so as to intersect with both data lines of said pair of data lines; a dummy line arranged so as to intersect with both data lines of said pair of data lines; a memory cell coupled to said word line and to at least one data line of said pair of data lines at a cross point of said word line and said at least one data line; a dummy cell coupled to said dummy word line and to at least one data line of said pair of data lines at a cross point of said dummy word line and said at least one data line; amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminal which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means; precharging means for setting said pair of data lines at an intermediate potential between said first reference voltage and said second reference voltage; and selecting means for selecting said word line and said dummy word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A semiconductor memory formed in a semiconductor integrated circuit comprising:
-
a pair of data lines; a word line arranged so as to intersect with one data line of said pair of data lines; a dummy word line arranged so as to intersect with the other data line of said pair of data lines; a memory cell coupled to said word line and to said one data line of said pair of data lines; a dummy cell coupled to said dummy word line and to said other data line of said pair of data lines; amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminals which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means; precharging means for setting said pair of data lines at an intermediate potential between a first reference voltage and a second reference voltage; and selecting means for selecting said word line and said dummy word line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A semiconductor memory formed in a semiconductor integrated circuit comprising:
-
a pair of data lines disposed substantially parallel and adjacent to each other; a word line arranged so as to intersect with both data lines of said pair of data lines; a dummy word line arranged so as to intersect with both data lines of said pair of data lines; a memory cell coupled to said word line and to at least one data line of said pair of data lines at a cross point of said word line and said at least one data line; a dummy cell coupled to said dummy word line and to at least one data line of said pair of data lines at a cross point of said dummy word line and said at least one data line; amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminals which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means, said amplifier means comprising first and second circuits; said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation; and said second circuit including a pair of crosscoupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation; precharging means for setting said pair of data lines at an intermediate potential between said first reference voltage and said second reference voltage; and selecting means for selecting said word line and said dummy word line, wherein the differential amplification operation of said first circuit is started at a time different from the time when the differential amplification operation of said second circuit is started. - View Dependent Claims (20, 21, 22, 23, 24, 25)
-
Specification