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Independent array grounds for flash EEPROM array with paged erase architechture

  • US 5,365,484 A
  • Filed: 08/23/1993
  • Issued: 11/15/1994
  • Est. Priority Date: 08/23/1993
  • Status: Expired due to Term
First Claim
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1. In a semiconductor integrated circuit memory device having array means formed of a plurality of half-sectors, each of said plurality of half-sectors (402, 404, . . . ) comprising:

  • a plurality of memory cells arrayed in rows (408-0 . . . 408-i) of word lines and columns (406-0 . . . 406-k) intersecting said rows of word lines, each of said memory cells including a floating gate transistor having a source, a drain, a floating gate, and a control gate;

    a plurality of half-sector bit line means each (SBL-0 . . . SBL-k) of said half-sector bit line means being connected to the drain of a memory cell in each of said rows so that said memory cells connected to said each half-sector bit line means form a column and said memory cells in said columns are connected to said plurality of half-sector bit line means in parallel;

    means (410-0 . . . 410-k) operatively coupled to said plurality of half-sector bit line means for selecting a half-sector;

    said control gates of said memory cells in each of said rows being connected to one of said word lines, said sources of said memory cells being connected to a separate individual ground line (412n);

    ground line circuit means (322) for generating a half-sector ground line signal (ARVSSnm), the non-selected sectors in said plurality of sectors being unaffected during erase operation on said selected sector; and

    said separate individual ground line being connected to said ground line circuit means for receiving said half-sector ground line signal.

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