Independent array grounds for flash EEPROM array with paged erase architechture
First Claim
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1. In a semiconductor integrated circuit memory device having array means formed of a plurality of half-sectors, each of said plurality of half-sectors (402, 404, . . . ) comprising:
- a plurality of memory cells arrayed in rows (408-0 . . . 408-i) of word lines and columns (406-0 . . . 406-k) intersecting said rows of word lines, each of said memory cells including a floating gate transistor having a source, a drain, a floating gate, and a control gate;
a plurality of half-sector bit line means each (SBL-0 . . . SBL-k) of said half-sector bit line means being connected to the drain of a memory cell in each of said rows so that said memory cells connected to said each half-sector bit line means form a column and said memory cells in said columns are connected to said plurality of half-sector bit line means in parallel;
means (410-0 . . . 410-k) operatively coupled to said plurality of half-sector bit line means for selecting a half-sector;
said control gates of said memory cells in each of said rows being connected to one of said word lines, said sources of said memory cells being connected to a separate individual ground line (412n);
ground line circuit means (322) for generating a half-sector ground line signal (ARVSSnm), the non-selected sectors in said plurality of sectors being unaffected during erase operation on said selected sector; and
said separate individual ground line being connected to said ground line circuit means for receiving said half-sector ground line signal.
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Abstract
An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.
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Citations
20 Claims
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1. In a semiconductor integrated circuit memory device having array means formed of a plurality of half-sectors, each of said plurality of half-sectors (402, 404, . . . ) comprising:
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a plurality of memory cells arrayed in rows (408-0 . . . 408-i) of word lines and columns (406-0 . . . 406-k) intersecting said rows of word lines, each of said memory cells including a floating gate transistor having a source, a drain, a floating gate, and a control gate; a plurality of half-sector bit line means each (SBL-0 . . . SBL-k) of said half-sector bit line means being connected to the drain of a memory cell in each of said rows so that said memory cells connected to said each half-sector bit line means form a column and said memory cells in said columns are connected to said plurality of half-sector bit line means in parallel; means (410-0 . . . 410-k) operatively coupled to said plurality of half-sector bit line means for selecting a half-sector; said control gates of said memory cells in each of said rows being connected to one of said word lines, said sources of said memory cells being connected to a separate individual ground line (412n); ground line circuit means (322) for generating a half-sector ground line signal (ARVSSnm), the non-selected sectors in said plurality of sectors being unaffected during erase operation on said selected sector; and said separate individual ground line being connected to said ground line circuit means for receiving said half-sector ground line signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a semiconductor integrated circuit memory device having array means formed of a plurality of half-sectors (402,404 . . . ), each of said plurality of half-sectors comprising:
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a plurality of memory cells arrayed in rows (408-0 . . . 408-i) of word lines and columns (406-0 . . . 406-k) intersecting said rows of word lines, each of said memory cells including a floating gate transistor having a source, a drain, a floating gate, and a control gate; a plurality of half-sector bit line means (SBL-0 . . . SBL-k) each of said half-sector bit line means being connected to the drain of a memory cell in each of said rows so that said memory cells connected to said each half-sector bit line means form a column and said memory cells in said columns are connected to said plurality of half-sector bit line means in parallel; means (410-0 . . . 410-k) operatively coupled to said plurality of half-sector bit line means for selecting a half-sector; said control gates of said memory cells in each of said rows being connected to one of said word lines, said sources of said memory cells being connected to a separate individual ground line (412n); a plurality of ground line circuit means (322) for generating multiple half-sector ground line signals (ARVSSnm), the non-selected sectors in said plurality of sectors being unaffected during erase operation on said selected sector; and said separate individual ground line being connected to an associated one of said plurality of ground line circuit means for receiving a corresponding one of said multiple half-sector ground line signals. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. In a semiconductor integrated circuit memory device having array means formed of a plurality of half-sectors, each of said plurality of half-sectors including a plurality of memory cells arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate, a control gate, a source region connected to a separate independent ground line, and a drain region coupled to a respective one of the bit lines, and where each memory cell is programmable predominately by transferring hot electrons into its floating gate and is erasable predominately by tunneling electrons from its floating gate to its source region, each of said plurality of half-sectors comprising:
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said control gate of each memory cell receiving a relatively negative potential during flash erasure; and ground line circuit means (322) for generating a half-sector ground line signal, (ARVSSnm) said separate independent ground line (412n) being connected to said ground line circuit means for receiving said half-sector ground line signal. - View Dependent Claims (20)
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Specification