Error-correction encoding and decoding system
First Claim
1. An error-correction code encoder, comprising:
- a first encoding section for encoding an Ip information series of (k1 ×
n2) digits having k1 digits in the first direction and n2 digits in the second direction to coded data containing check symbols each having a length of (n1 -k1) digits in the first direction;
a second encoding section for encoding an Is information series of (r×
k3) digits (where r≦
n1 -k1 and k3 <
n2) to data containing check symbols each having a length of (n2 -k3) digits in the second direction;
a buffer memory for storing the data and check symbols of both information series; and
an encoding control means for controlling said first and second encoding sections and said buffer memory to cause, when an Ip information series is input to said buffer memory, coded data encoded by said first encoding section to be output from said buffer memory, and, when both Ip information series and Is information series are input to said buffer memory, said first encoding section to encode the Ip information series, said second encoding section to encode the Is information series and said buffer memory to delete the check symbols of (r×
n2) digits of the coded data encoded by said first encoding section and to output the remaining digits of the coded data encoded by said first encoding section and the data of (r×
n2) digits of the coded data encoded by said second encoding section.
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Abstract
The present invention provides an error-correction code encoding and decoding technique in which an information amount is variable in a block, and error-correction encoding in the block can be done efficiently without a substantial change in circuit configuration regardless of information amount. An encoder comprises a C1 encoding section for encoding an Ip information series, a C3 encoding section for encoding an Is information series, a control circuit for controlling the encoding sections based on an identification signal indicating whether the Is information series is contained, and a buffer memory. If an Is information series is contained, an area corresponding to the Is information series is deleted from check symbols of the Ip information series and replaced with coded data of the Is information series. A decoder decodes a received word thus encoded. This obviates superimposition-separation of C3 information, thereby realizing efficient error-correction encoding in a block, while maintaining an information amount of a block variable, without any change in circuit configuration based on information amount.
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Citations
17 Claims
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1. An error-correction code encoder, comprising:
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a first encoding section for encoding an Ip information series of (k1 ×
n2) digits having k1 digits in the first direction and n2 digits in the second direction to coded data containing check symbols each having a length of (n1 -k1) digits in the first direction;a second encoding section for encoding an Is information series of (r×
k3) digits (where r≦
n1 -k1 and k3 <
n2) to data containing check symbols each having a length of (n2 -k3) digits in the second direction;a buffer memory for storing the data and check symbols of both information series; and an encoding control means for controlling said first and second encoding sections and said buffer memory to cause, when an Ip information series is input to said buffer memory, coded data encoded by said first encoding section to be output from said buffer memory, and, when both Ip information series and Is information series are input to said buffer memory, said first encoding section to encode the Ip information series, said second encoding section to encode the Is information series and said buffer memory to delete the check symbols of (r×
n2) digits of the coded data encoded by said first encoding section and to output the remaining digits of the coded data encoded by said first encoding section and the data of (r×
n2) digits of the coded data encoded by said second encoding section. - View Dependent Claims (3, 4)
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2. An error-correction code encoding method, comprising the steps of:
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encoding an Ip information series of (k1 ×
n2) digits having k1 digits in the first direction and n2 digits in the second direction to coded data containing check symbols each having a length of (n1 -k1) digits in the first direction;encoding an Is information series of (r×
k3) digits where r≦
n1 -k1 and k3 <
n2) to data containing check symbols each having a length of (n2 -k3) digits in the second direction;storing the data and check symbols of both information series; and causing, when an identification signal indicates that an Ip information series is input to said buffer memory, the coded data encoded by said first encoding section to be output from said buffer memory, and, when an identification signal indicates that both Ip information series and Is information series are input to said buffer memory, said first encoding section to encode the Ip information series, and the second encoding section to encode the Is information series and said buffer memory to output data including the coded data encoded by said first encoding section and the data of (r×
n2) digits of the coded data encoded by said second encoding section,check symbols of (r×
n2) digits of the coded data encoded by said first encoder being not stored in said buffer memory when the Ip information series and the Is information series are encoded.
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5. An error-correction code encoder, comprising:
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a first encoding section for encoding an Ip information series to first coded data including first check symbols; a second encoding section for encoding an Is information series to second coded data including second check symbols, wherein said second coded data includes fewer digits than said first check symbols; and a buffer memory for storing said first and second coded data, such that a portion of said first check symbols is deleted and replaced by said second coded data. - View Dependent Claims (6, 7)
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8. An error-correction code encoding method, comprising the steps of:
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encoding an Ip information series to first coded data including first check symbols; encoding an Is information series to second coded data including second check symbols, wherein said second coded data includes fewer digits than said first check symbols; deleting a portion of said first check symbols; and replacing said deleted portion of said first check symbols with said second coded data. - View Dependent Claims (9, 10, 11)
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12. A decoder for decoding encoded data including first data encoding an Ip information series and second data encoding an Is information series, a portion of check symbols of said first data being deleted and replaced by said second data in said encoded data when an Is information series is encoded, said decoder comprising:
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a first decoding section for decoding a portion of said encoded data corresponding to said first data to provide an Ip information series; and a second decoding section for decoding a portion of said encoded data corresponding to said second data to provide an Is information series. - View Dependent Claims (13, 14)
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15. A method for decoding encoded data including first data encoding an Ip information series and second data encoding an Is information series, a portion of check symbols of said first data being deleted and replaced by said second data in said encoded data when an Is information series is encoded, said method comprising the steps of:
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decoding a portion of said encoded data corresponding to said first data to provide an Ip information series; decoding a portion of said encoded data corresponding to said second data to provide an Is information series. - View Dependent Claims (16, 17)
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Specification