Transmitting circuit and receiving circuit

• US 5,365,543 A
• Filed: 09/27/1993
• Issued: 11/15/1994
• Est. Priority Date: 12/09/1991
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Kenichi, Ohnishi, Hiroshi, Takeishi, Minako
• Primary Examiner(s): Swann, Tod R.
• Application Number:
  US08/127,276
• Time in Patent Office: 414 Days
• Field of Search: 375/1, 380/34
• US Class Current: 375/145
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

In a first direct-sequence spread spectrum communication system having a transmission circuit where a data signal to be transmitted is coded by a first chip code signal and a receiving circuit for decoding the transmitted data signal with a second chip code signal, the synchronization between the said first and second chip code signals is performed when an asynchronous condition of said first and second chip code signals is detected over a predetermined interval. In a second direct-sequence spread spectrum communication system having a transmission circuit where a data signal having a variable data rate V to be transmitted is coded by a first chip signal having a data rate C and coded by a reference code signal having a data rate R, C>V, R>V. A receiving circuit receives the data signal from the above-mentioned transmission circuit decoded by a second chip signal and a second reference code signal. This receiving circuit has a lowpass filter and it is unnecessary to change the lowpass filter if the data rate V is lower than R. A third system combines these techniques.

Claims

1. A receiving circuit for receiving a transmitted data signal which is coded by a first chip code signal having a predetermined signal pattern to spread spectrum of the transmitted data and is modulated by a carrier signal, said receiving circuit comprising:

(a) receiving means for receiving said transmitted data signal;

(b) demodulation means for demodulating said received data signal;

(c) chip code signal generation means for generating a second chip code signal having said predetermined signal pattern;

(d) decoding means for decoding said demodulated data signal with said second chip code signal;

(e) detection means for detecting whether said second chip code signal is in an asynchronous condition with said received data signal to produce an asynchronous detection signal;

(f) synchronizing means for synchronizing said second chip code signal with said first chip code signal included in said received data signal in response to said asynchronous detection signal; and

(g) control means responsive to said detection means for measuring a time interval for which said asynchronous detection signal is produced continuously and for supplying said asynchronous detection signal to said synchronizing means when said time interval is longer than a predetermined interval.

2. A receiving circuit as claimed in claim 1, wherein said synchronizing means has phase shifting means for successively phase shifting said second chip code signal in the presence of said asynchronous detection signal to detect a synchronous condition between said first chip signal included in the received signal and the second chip signal.

3. A transmitting circuit for transmitting a data signal having variable data rate, comprising:

(a) first coding means for coding said data signal with a first coding signal having a first predetermined signal pattern and a first data rate;

(b) second coding means for coding said data signal with a second coding signal having a second predetermined signal pattern and a second data rate; and

(c) modulation means for modulating said data signal coded by said first and second coding signals, said second data rate is higher than said variable data rate in order to spread spectrum of said data signal, said second data rate is higher than said first data rate in order to provide a lower limitation of a data rate of said data signal coded by said first coding means.

4. A receiving circuit for receiving a transmitted data signal which has a variable data rate V and is coded by a first chip code signal having a first predetermined signal pattern to spread spectrum of the transmitted data and a data rate C, said transmitted data being coded by a first reference code signal having a second predetermined signal pattern and having a data rate R, said transmitted data signal being modulated by a carrier signal said data rate C being higher than said variable data rate V in order to spread spectrum of said data signal, said data rate R being higher than said variable data rate V in order to provide a limitation of a data rate of said data signal coded by said reference code signal, said receiving circuit comprising:

(a) receiving means for receiving said transmitted data signal;

(b) demodulation means for demodulating said received data signal;

(c) chip code signal generation means for generating a second chip code signal having said predetermined signal pattern;

(d) decoding means for decoding said demodulated data signal with said second chip code signal;

(e) detection means for detecting whether said second chip code signal is in an asynchronous condition with said received data signal to produce an asynchronous detection signal;

(f) synchronizing means for synchronizing said second chip code signal with said first chip code signal included in said received data signal in response to said asynchronous detection signal;

(g) reference code signal generation means for generating a second reference code signal having said predetermined signal pattern; and

(h) second decoding means for decoding said demodulated data signal with said second reference code signal.

5. A receiving circuit as claimed in claim 4, wherein said synchronizing means has phase shifting means for successively phase shifting said second chip code signal in the presence of said asynchronous detection signal to detect a synchronous condition between said first chip signal included in the received signal and the second chip signal.

6. A receiving circuit as claimed in claim 4, further comprising:

(a) second detection means for detecting whether said second reference code signal is in an asynchronous condition with said received data signal to produce a second asynchronous detection signal;

(b) second synchronizing means for synchronizing said second reference code signal with said first reference code signal included in said received data signal in response to said second asynchronous detection signal; and

(c) second control means responsive to said second detection means for measuring a second time interval for which said second asynchronous detection signal is produced continuously and for supplying said second asynchronous detection signal to said second synchronizing means when said second time interval is longer than a second predetermined interval.

7. A receiving circuit for receiving a transmitted data signal which has a variable data rate V and is coded by a first chip code signal having a first predetermined signal pattern to spread spectrum of the transmitted data and a data rate C, said transmitted data being coded by a first reference code signal having a second predetermined signal pattern and having a data rate R, said transmitted data signal being modulated by a carrier signal, said data rate C being higher than said variable data rate V in order to spread spectrum of said data signal, said data rate R being higher than said variable data rate V in order to provide a limitation of a data rate of said data signal coded by said reference code signal, said receiving circuit comprising:

(a) receiving means for receiving said transmitted data signal;

(b) demodulation means for demodulating said received data signal;

(c) chip code signal generation means for generating a second chip code signal having said predetermined signal pattern;

(d) decoding means for decoding said demodulated data signal with said second chip code signal;

(e) detection means for detecting whether said second chip code signal is in an asynchronous condition with said received data signal to produce an asynchronous detection signal;

(f) synchronizing means for synchronizing said second chip code signal with said first chip code signal included in said received data signal in response to said asynchronous detection signal;

(g) control means responsive to said detection means for measuring a time interval for which said asynchronous detection signal is produced continuously and for supplying said asynchronous detection signal to said synchronizing means when said time interval is longer than a predetermined interval;

(h) reference code signal generation means for generating a second reference code signal having said predetermined signal pattern; and

(i) second decoding means for decoding said demodulated data signal with said second reference code signal.

8. A receiving circuit as claimed in claim 7, wherein said synchronizing means has phase shifting means for successively phase shifting said second chip code signal in the presence of said asynchronous detection signal to detect a synchronous condition between said first chip signal included in the received signal and the second chip signal.

9. A receiving circuit as claimed in claim 7, further comprising:

(a) second detection means for detecting whether said second reference code signal is in an asynchronous condition with said received data signal to produce a second asynchronous detection signal;

(b) second synchronizing means for synchronizing said second reference code signal with said first reference code signal included in said received data signal in response to said second asynchronous detection signal; and

(c) second control means responsive to said second detection means for measuring a second time interval for which said second asynchronous detection signal is produced continuously and for supplying said second asynchronous detection signal to said second synchronizing means when said second time interval is longer than a second predetermined interval.