Vertical power MOSFET structure having reduced cell area

• US 5,366,914 A
• Filed: 01/29/1993
• Issued: 11/22/1994
• Est. Priority Date: 01/29/1992
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Takahashi, Mitsuasa, Kubota, Hitoshi, Takahashi, Nobumitsu
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MASON, DAVID
• Application Number:
  US08/011,151
• Time in Patent Office: 662 Days
• Field of Search: 437/200, 437/203, 437/913, 437/41, 257/330
• US Class Current: 438/270
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a vertical power field effect transistor, a side surface of a gate electrode is covered with a side oxide film, and a groove is formed in self-alignment with the side oxide film to extend from a surface area of a silicon substrate between a pair of adjacent gate electrodes, to reach a base region. A tungsten film is filled into the groove thus formed, and a source electrode-is formed in contact with the tungsten film within the groove.

Claims

1. A method for manufacturing a vertical power field effect transistor comprising the steps of:

forming a first insulating film covering on a principal surface of a semiconductor substrate of a first conductivity type;

forming a conducting layer on said first insulating film;

forming a first interlayer insulating film covering said conducting layer;

patterning a stacked structure formed of said first insulating film, said conducting layer and said first interlayer film so as to form a patterned stacked structure and to expose a portion of said substrate uncovered by said patterned stacked structure, said first insulating film of said patterned stacked structure forming a gate insulator film, said conducting layer of said patterned stacked structure forming a gate electrode;

introducing an impurity of a second conductivity type opposite to said first conductivity type into said exposed portion of said substrate by using the patterned stacked structure as a mask, so that a base region extending under said gate electrode is formed;

introducing an impurity of said first conductivity type by using the patterned stacked structure as a mask, so that a source region smaller than said base region is formed in said base region and extends under said gate electrode;

forming a second interlayer insulating film on said principal surface of said substrate;

anisotropically etching said second interlayer insulating film so as to form a side insulating film which covers only each side surface of the gate electrode and the gate insulator film;

anisotropically etching said substrate by using the side insulating films as a mask, so as to form, in a self-alignment manner, a groove which extends downward from said principal surface of said silicon substrate to pass through said source region and to reach said base region;

filling said groove with a metal film;

forming a metal film evaporated on the entire resulting surface; and

patterning said metal film to form a source electrode which is electrically connected to said metal filled in said groove.

2. A method for manufacturing a vertical power field effect transistor comprising the steps of:

forming a drain layer of a first conductivity type at an upper surface of a semiconductor substrate of said first conductivity type;

forming at an upper surface of said drain layer a base layer of a second conductivity type opposite to said first conductivity type;

forming a source layer of said first conductivity type at an upper surface of said base layer;

forming in said substrate a plurality of vertical trenches separated from each other and passing through said source layer and said base layer to reach said drain layer;

forming a gate oxide film covering said principal surface of said substrate and an inner surface of said trenches;

forming a gate electrode layer covering said gate oxide film at said principal surface of said substrate and within said trenches;

forming a first interlayer insulating film on said gate electrode layer at said principal surface of said substrate and within said trenches;

patterning a stacked structure composed of said gate oxide film, said gate electrode layer and said first interlayer insulating film so as to form a pattern stacked structure and to expose a portion of said substrate, said gate electrode layer of said patterned stacked structure forming a gate electrode;

forming a second interlayer insulating film on said principal surface of said substrate;

anisotropically etching said second interlayer insulating film so as to form a side insulating film which covers only each side surface of the gate electrode, the gate insulator film and the remaining first interlayer insulating film;

anisotropically etching said substrate by using the side insulating films as a mask, so as to form, in a self-alignment manner, a groove which extends downward from said principal surface of said substrate to pass through said source region and to reach said base region;

filling said groove with a metal film;

forming a metal film evaporated on the entire resulting surface; and

patterning said metal film to form a source electrode which is electrically connected to said metal filled in said groove.