Microchip assembly with electrical element in sealed cavity

• US 5,367,194 A
• Filed: 04/23/1992
• Issued: 11/22/1994
• Est. Priority Date: 10/29/1990
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Beatty, Christopher C.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/872,467
• Time in Patent Office: 943 Days
• Field of Search: 257/690, 257/692, 257/700, 257/704, 257/710, 257/701, 257/727, 338/314, 338/311, 338/310, 338/207, 338/307, 338/237
• US Class Current: 257/727
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of producing a microchip having at least a portion of an electrical circuit element contained within a hermetically sealed enclosure comprising the steps of: forming a cavity in a first substrate assembly which has a cavity opening at a first surface portion of the first substrate assembly; forming an electrical circuit element and sealing ring from a film applied to a first surface portion of a second substrate assembly with the sealing ring arranged in circumscribing relationship with at least a portion of the circuit element; positioning the first surface portion of the first substrate assembly opposite the first surface portion of the second substrate assembly with the sealing ring located in circumscribing relationship with the cavity opening; sealingly bonding the sealing ring to the first surface portion of the first substrate assembly.

Claims

1. A microchip assembly comprising:

a first substrate assembly having a generally planar exterior surface portion and having a cavity therein with an opening encompassed by said planar exterior surface portion;

a second substrate assembly having a generally planar exterior surface portion positioned in opposite parallel relationship with said exterior surface portion of said first substrate assembly;

a patterned conductive film layer sandwiched between said exterior surface portions of said first and second substrate assemblies comprising;

a sealing ring portion positioned in continuous circumscribing relationship with said cavity opening and continuous engaging relationship with said exterior surface portions of said first and second substrate assemblies and sealingly bonded thereto;

an electrical circuit element portion, having at least a part thereof encompassed by said sealing ring portion, bonded to said exterior surface portion of said second substrate assembly.

2. The invention of claim 1 wherein said patterned film layer is of a constant thickness.

3. The invention of claim 1 wherein said sealing ring portion intersects said electrical circuit element portion.

4. The invention of claim 3 wherein said sealing ring portion is positioned immediately adjacent the periphery of said cavity opening.

5. The invention of claim 3 wherein said circuit element portion comprises terminal end pads positioned on said generally planar exterior surface portion of said second substrate assembly which are not circumscribed by said sealing ring portion.

6. The invention of claim 1 wherein said electrical circuit portion is not intersected by said sealing ring portion and is entirely circumscribed thereby.

7. A device comprising:

a first substrate assembly having a generally planar exterior surface portion and having a cavity therein with an opening encompassed by said first surface portion;

a second substrate assembly having a generally planar exterior surface portion positioned in opposite parallel relationship with said exterior surface portion of said first substrate assembly;

a patterned conductive film layer sandwiched between said exterior surface portions of said first and second substrate assemblies comprising;

a sealing ring portion positioned in continuous circumscribing relationship with said cavity opening and continuous engaging relationship with said exterior surface portions of said first and second substrate assemblies and sealingly bonded thereto;

an electrical circuit element portion, having at least a part thereof encompassed by said sealing ring portion, bonded to said exterior surface portion of said second substrate assembly.