Field programmable gate array for synchronous and asynchronous operation

• US 5,367,209 A
• Filed: 04/30/1993
• Issued: 11/22/1994
• Est. Priority Date: 01/07/1992
• Status: Expired due to Fees

• Current Assignee: University of Washington
• Original Assignee: University of Washington
• Inventors: Burns, Steven M., Borriello, Gaetano, Ebeling, William H. C., Hauck, Scott A.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/056,434
• Time in Patent Office: 571 Days
• Field of Search: 307/465-469, 340/825.83
• US Class Current: 326/45
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.

Claims

1. A field programmable gate array (FPGA) having at least one logic block, each of said logic blocks having inputs for receiving a plurality of input signals and outputs for outputting a plurality of output signals, the FPGA further comprising:

(a) at least one arbiter block, said arbiter block having inputs for receiving a plurality of input signals and outputs for outputting a plurality of output signals, and wherein said arbiter block is programmable to provide an arbiter function, an enabled arbiter function, or a synchronizer function; and

(b) interconnect resources for providing electrical communication between said inputs of either said arbiter blocks or logic blocks and the outputs of either said arbiter blocks or logic blocks.

2. The FPGA of claim 1 wherein said logic blocks are further capable of calculating logical functions and routing of said input signals.

3. The FPGA of claim 1 wherein said arbiter blocks are further capable of routing said input signals.

4. The FPGA of claim 1 wherein the ratio of said arbiter blocks to said logic blocks is between 5% and 10%.

5. A method of providing a field programmable gate array (FPGA) for synchronous and asynchronous operation, said FPGA comprising a plurality of logic blocks, each of said logic blocks having inputs for receiving a plurality of input signals and outputs for outputting a plurality of output signals, said method comprising the step of:

(a) replacing at least one of said logic blocks with an arbiter block, said arbiter block having inputs for receiving a plurality of input signals and outputs for outputting a plurality of output signals.

6. The method of claim 5 wherein said replacement of said logic blocks is done in a random nature.

7. The method of claim 6 wherein 5% to 10% of said logic blocks are replaced by said arbiter blocks.

8. A field programmable gate array comprising:

(a) a plurality of forwardly propagating routing and logic blocks (FPRLBs), each of said FPRLBs having inputs for receiving a plurality of input signals and outputs for outputting a plurality of output signals; and

(b) a plurality of backwardly propagating routing and logic blocks (BPRLBs), each of said BPRLBs having inputs for receiving a plurality of input signals and outputs for outputting a plurality of output signals, said BPRLBs intermeshing with said FPRLBs to form a two-dimensional checkerboard array, wherein the columns of said checkerboard array comprise a plurality of FPRLBs and BPRLBs arranged in alternating sequence and the rows of said checkerboard array comprise a plurality of FPRLBs and BPRLBs arranged in alternating sequence;

wherein each of said FPRLBs not on the periphery of said checkerboard array is communicatively connected to a plurality of BPRLBs in the same column such that said input signals and said output signals may be passed therebetween, wherein each of said BPRLBs not on the periphery of said checkerboard array is communicatively connected to a plurality of FPRLBs in the same column such that said input signals and said output signals may be passed therebetween, wherein each of said FPRLBs not on the periphery of said checkerboard array is communicatively connected to a plurality of FPRLBs in the immediately adjacent leftward column such that said input signals may be received therefrom and a plurality of FPRLBs in the immediately adjacent rightward column such that said output signals may be transmitted thereto, and wherein each of said BPRLBs not on the periphery of said checkerboard array is communicatively connected to a plurality of BPRLBs in the immediately adjacent leftward column such that said output signals may be transmitted thereto and a plurality of BPRLBs in the immediately adjacent rightward column such that said input signals may be received therefrom;

further wherein a predetermined ratio of said FPRLBs and BPRLBs is substituted therefore by a plurality of routing and arbiter blocks (RABs).

9. The apparatus of claim 8, further including a plurality of segmented routing channels, said segmented routing channels disposed between the columns of said checkerboard array, said segmented routing channels for receiving said output signals from and providing said input signals to said FPRLBs and BPRLBs in the columns of said checkerboard array immediately adjacent to the individual said segmented routing channels.

10. The apparatus of claim 9, wherein each of said FPRLBs not on the periphery of said checkerboard array provides said output signals to and receives said input signals from two said BPRLBs in the same column and that are directly adjacent above and below;

and

wherein each of said BPRLBs not on the periphery of said checkerboard array provides said output signals to and receives input signals from two said FPRLBs in the same column and that are directly adjacent above and below.

11. The apparatus of claim 9, wherein each of said FPRLBs not on the periphery of said checkerboard array provides said output signals to two said FPRLBs located in the immediately adjacent rightward column and that are in adjacent rows immediately above and below;

wherein each of said FPRLBs not on the periphery of said checkerboard array receives said input signals from two said FPRLBs located in the immediately adjacent leftward column and that are in adjacent rows immediately above and below;

wherein each of said BPRLBs not on the periphery of said checkerboard array provides said output signals to two said BPRLBs located in the immediately adjacent leftward column and that are in adjacent rows immediately above and below; and

wherein each of said BPRLBs not on the periphery of said checkerboard array receives said input signals from two said BPRLBs located in the immediately adjacent rightward column and that are in adjacent rows immediately above and below.

12. The apparatus of claim 9, wherein said segmented routing channels include a forwardly propagating segmented routing channel (FPSRC) and a backwardly propagating segmented routing channel (BPSRC);

said FPSRC for receiving said output signals from said FPRLBs in the immediately adjacent leftward column and providing said input signals to said FPRLBs in the immediately adjacent rightward column; and

said BPSRC for receiving said output signals from said BPRLBs in the immediately adjacent rightward column and providing said input signals to said BPRLBs in the immediately adjacent leftward column.

13. The apparatus of claim 12, wherein both said FPSRCs and said BPSRCs include a plurality of separate segmented bus lines.

14. The apparatus of claim 13 wherein said FPSRCs and said BPSRCs share at least one bus line.

15. The apparatus of claim 9, wherein said FPRLBs and said BPRLBs are programmable to provide said output signals as a logic function of said input signals;

and

wherein said FPRLBs and said BPRLBs are programmable to route said input signals that are received to other said FPRLBs and said BPRLBs.

16. The apparatus of claim 15, further including a plurality of I/O pads disposed along the side periphery of said field programmable gate array, said I/O pads for receiving said output signals from and providing said input signals to the FPRLBs and BPRLBs disposed in the left most and right most columns of said checkerboard array.

17. The apparatus of claim 16, further including a plurality of routing channel I/O pads disposed along the top and bottom periphery of said checkerboard array, said I/O pads for providing said input signals to and receiving output signals from said segmented routing channels.

18. The apparatus of claim 17, further including a plurality of top-bottom I/O pads disposed along the top and bottom periphery of said checkerboard array for providing said input signals to and receiving said output signals from said FPRLBs and BPRLBs disposed in the top most and bottom most rows of said checkerboard array.