Video codec, for a videophone terminal of an integrated services digital network

• US 5,367,331 A
• Filed: 02/23/1993
• Issued: 11/22/1994
• Est. Priority Date: 02/24/1992
• Status: Expired due to Term

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Rasse, Yves, Freund, Christian, Secher, Fernand, Thiberville, Jean, Douhet, Gerard
• Primary Examiner(s): Chan, Wing F.
• Application Number:
  US08/021,042
• Time in Patent Office: 637 Days
• Field of Search: 379/53, 379/54, 379/93, 379/96-98, 358/85, 358/105, 358/141, 358/186, 348/14, 348/17-19, 348/22, 348/24, 348/467, 348/723
• US Class Current: 348/14.01
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: H04N 7/148 Interfacing a video terminal to a particular transmission medium, e.g. ISDN

Abstract

A video codec for a videophone terminal of an integrated services digital network. The codec is organized to receive firstly image signals from a television camera so as to transmit them, after compressing and encoding them, to a remote video decoding unit, via a digital transmission line, and secondly similarly-processed image signals via the digital transmission line, so as to decompress and decode them for a television screen receiver locally connected to the video codec. The video codec includes a processing unit, of the integrated circuit type, co-operating with a single external memory plane both to compress and encode data to be transmitted, and also to decompress and decode received data, with the assistance of internal operational components time shared so as to apply known methods to transmission and to reception.

Claims

1. A video codec particularly for videophone applications, and more particularly for a videophone terminal of an integrated services digital network, said codec being organized to receive firstly image signals coming from a local television camera so as to transmit them, after compressing and encoding them, to a compatible remote video decoding unit, in particular of another video codec, via a digital transmission line, in particular of the telephone type, and secondly image signals similarly compressed and encoded by a remote video encoding unit, in particular of said other video codec, the similarly compressed image signals being received via the digital transmission line, and then being decompressed and decoded for a television screen receiver locally connected to said video codec, wherein said video codec includes a processing unit co-operating with a single external memory plane both to compress and encode data to be transmitted, and also to decompress and decode received data, with the assistance of time-shared internal operational components;

wherein the processing unit includes a discrete cosine transform operator and a quantifier connected together in series and time shared in association with a loop filter firstly, directly and then inversely as regards the assembly comprising the transform operator and the quantifier, for processing macroblocks of image to be transmitted, and secondly, inversely as regards said assembly, for processing macroblocks of received image.

2. A video codec according to claim 1, wherein the processing unit including the quantifier and the discrete cosine transform operator connected together in series and time shared, also includes an inter-intra selection and movement estimation circuit and two read/write reference memories connected to the bus link, in the same way as the operator and the quantifier mentioned above, and simultaneously time shared for transmission, the first memory successively storing a macroblock of incident image to be processed for transmission, as obtained from the external main memory, and then the corresponding quantified prediction obtained when the quantifier works directly, and the second memory successively storing the preceding image zone, in which the macroblock to be processed is sought, as supplied by the external main memory, and then the result obtained after any displacement of the processed macroblock under the action of the movement estimation circuit connected via a first input to the first reference memory, via a second input to the second reference memory, and via an output to an addressing auxiliary of the second reference memory.

3. A video codec according to claim 1, wherein the processing unit including the quantifier and the discrete cosine transform operator connected together in series and time shared, also includes a read/write scanning conversion memory time shared for successively making it possible firstly to obtain data relating to significant transformation coefficients of a block identified by scanning, preferably in zigzag, on the basis of transformation coefficients received by said memory from the quantifier operating directly for transmission, and secondly to perform the inverse conversion on reception on the basis of the positioning data by reference to the selected scanning, and on the basis of the associated amplitude data, received via the digital line and via a buffer reception sector of the external main memory.

4. A video codec according to claim 1, including a single memory plane connecting an external main memory to an integrated circuit including the processing unit via a multifilament bus link which serves, in particular, the processing unit, said memory organized for temporary image storage, respectively for the purposes of transmission, reception, and processing before transmission or after reception, as well as for local inserting purposes, being write and read addressed by an addressing auxiliary included in the integrated circuit and specifically connected to the memory.

5. A video codec according to claim 4, wherein the external main memory is connected to an addressing auxiliary which is incorporated into the integrated circuit, and which performs firstly separate read and write addressing in two fixed zones, one of which forms a buffer for the processed image signals to be transmitted over the digital line, and the other of which forms a buffer for the signals received via the digital line and to be processed, and secondly separate addressing in analogous manner in three storage sectors for storing image to be transmitted, one of which sectors is assigned to storing the camera image data being acquired, and the other two sectors, which are interchangeable, are assigned to storing previously processed image data and image data as being obtained by processing, as well as separate addressing in analogous manner in three interchangeable transmitted image storage sectors, one sector being assigned to storing the data of an image being received, and the two other sectors being assigned to storing the data of the previously received image under reconstruction and preferably of the image previously reconstructed and in the course of being sent to the local television screen receiver.

6. A video codec according to claim 4, wherein the external main memory is connected via the bus link both to the processing unit included in the integrated circuit, and also to the output of a video multiplexing and entropy encoding circuit which is included in the integrated circuit, which receives the image data coming from the processing unit to be transmitted over the digital line, and which is controlled by an inter-intra selection and movement estimation circuit of said processing unit.

7. A video codec according to claim 4, wherein the external main memory is also connected via the bus link to the digital line via an error correction code insertion circuit, on transmission, and via an error correction and framing recovery circuit, via an entropy decoding and video demultiplexing circuit, on reception, said circuits being provided in the integrated circuit with the processing unit.

8. A video codec according to claim 4, wherein the external main memory, of the VIDEORAM type, which is connected via a first port to the bus link, is connected via a second port, of the series type, to two video standards converters respectively performing conversion to an intermediate format for processing the video signals received from the local camera, for the purposes of transmission over the digital line, and the inverse conversion for the signals processed by the codec for the television screen receiver locally connected thereto.

9. A video codec according to claim 4, wherein the external main memory, of the DRAM type, is connected via the bus link both to the processing unit of the integrated circuit and to the video standards converters respectively performing the conversion of video signals received from the local camera to an intermediate format so that they can be processed, and the inverse conversion for the signals supplied by the processing unit for the local television screen receiver.