Randomly accessible memory having time overlapping memory accesses

• US 5,367,494 A
• Filed: 08/31/1993
• Issued: 11/22/1994
• Est. Priority Date: 05/20/1991
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Alsup, Mitchell K., Scales, Hunter L., Shebanow, Michael C., Hoekstra, George P.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/113,632
• Time in Patent Office: 448 Days
• Field of Search: 365/230.03, 365/230.05, 365/230.06, 365/230.08, 365/189.04, 365/189.05, 365/193
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.

Claims

1. An integrated circuit, comprising:

an address bank decoder for decoding an address bank signal to provide a first one of a plurality of bank enable signals, the address bank decoder having an input for receiving the address bank signal and a plurality of outputs wherein each of the plurality of outputs provides a respective one of the plurality of bank enable signals;

an input data decoder for decoding an input data bank signal to provide a first one of a plurality of input enable signals, the input data decoder having an input for receiving the input data bank signal and a plurality of outputs wherein each of the plurality of outputs provides a respective one of the input enable signals;

an output data decoder for decoding an output data bank signal to provide a first one of a plurality of output enable signals, the output data decoder having an input for receiving the output data bank signal and a plurality of outputs wherein each of the plurality of outputs provides a respective one of the output enable signals; and

a plurality of memory banks wherein each of the plurality of memory banks is concurrently accessible, each of the plurality of memory banks, comprising;

a first latch for selectively storing a first address value in response to a first enable signal;

a second latch for selectively storing a first data value in response to a second enable signal;

a third latch for selectively storing a second data value in response to a third enable signal;

a fourth latch for selectively storing a first control value in response to a fourth enable signal;

logic means for selectively asserting the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal when a corresponding one of the plurality of bank enable signals is in a predetermined logic state, the logic means being coupled to each of the first latch, the second latch, the third latch, and the fourth latch; and

an array of memory storage elements for selectively communicating a digital information value, the array of memory storage elements being coupled to each of the first latch, the second latch, the third latch, and the fourth latch;

wherein a first one of the plurality of memory banks executes a first data communication operation subsequent to latching the first address value, the first control value, and one of the first and second data values and a second one of the plurality of memory banks executes a second data communication operation subsequent to latching a second address value, a second control value, and a third data value, the second one of the plurality of memory banks executing the second data communication operation concurrently with the first one of the plurality of memory banks executing the first data communication operation.

2. The integrated circuit of claim 1 wherein the first control signal indicates that the first one of the plurality of memory banks should perform one of a read and a write data operation and the second control signal indicates that the second one of the plurality of memory banks perform one of the read and the write data operation.

3. The integrated circuit of claim 1 wherein the first address value stored in the first latch of a first one of the plurality of memory banks corresponds to a first memory storage element in the array of memory storage elements.

4. The integrated circuit of claim 3 wherein when the first control signal is in a first logic state, the first memory storage element is enabled to perform a memory read operation and when the first control signal is in a second logic state, the first memory storage element to perform a memory write operation.

5. The integrated circuit of claim 1 wherein the logic means logically combines the corresponding one of the plurality of bank enable signals and an address strobe signal to provide the first latch signal.

6. The integrated circuit of claim 1 wherein the logic means logically combines a corresponding one of the plurality of data input bank enable signals and a data input strobe signal to provide the second latch signal.

7. The integrated circuit of claim 1 wherein the logic means logically combines a corresponding one of the plurality of data output bank enable signals and a data output strobe signal to provide the third latch signal.

8. The integrated circuit of claim 1 wherein the logic means logically combines the corresponding one of the plurality of bank enable signals and an address strobe signal to provide the fourth latch signal.

9. A method for accessing a memory in an integrated circuit, comprising the steps of:

receiving a first instruction for executing a first memory operation, the first instruction indicating a first memory location;

decoding the first instruction to indicate a first one of a plurality of memory banks to be accessed during execution of the first memory operation;

storing a first address value in a first latch circuit in the first one of the plurality of memory banks, the first address value corresponding to a first memory location in the first one of the plurality of memory banks;

storing a first control value in a second latch circuit in the first one of the plurality of memory banks, the first control value indicating a type of memory operation to be executed, the type of memory operation being one of a read memory operation and a write memory operation;

receiving a second instruction for executing a second memory operation, the second instruction indicating a second memory location to be accessed;

decoding the second instruction to indicate a second one of the plurality of memory banks to be accessed during execution of the second memory operation;

storing a second address value in a first latch circuit in the second one of the plurality of memory banks, the second address value corresponding to a second memory location in the second one of the plurality of memory banks;

storing a second control value in a second latch circuit in the second one of the plurality of memory banks, the second control information value indicating the type of memory operation to be executed; and

concurrently executing the first memory operation in the first one of the plurality of memory banks and the second memory operation in the second one of the plurality of memory banks.

10. The method of claim 9 further comprising the steps of:

storing a first data value in a third latch circuit of the first one of the plurality of memory banks;

enabling the third latch circuit to output the first data value to a driver circuit when the first control information indicates that the first memory operation is the write memory operation;

enabling the first latch circuit to output the first address value stored therein;

accessing the first memory location in the first one of the plurality of memory banks in response to the first address value; and

writing the first data value in the first memory location.

11. The method of claim 10 further comprising the steps of:

enabling the first latch circuit to output the first address value stored therein;

accessing a stored data value from the first memory location in the first one of the plurality of memory banks in response to the first address value;

storing the stored data value in a fourth latch circuit when the first control information indicates that the first memory operation is the read memory operation;

enabling the fourth latch circuit to providing the stored data value to an output driver circuit; and

enabling the output driver circuit to provide the stored data value in response to an external data output control value.