Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets

• US 5,367,643 A
• Filed: 02/06/1991
• Issued: 11/22/1994
• Est. Priority Date: 02/06/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Meleis, Hanafy E., Seidman, David I., Chang, Paul, Delp, Gary S., Montalvo, Rafael M., Zumbo, Dominick A., Tantawy, Ahmed N.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Harrity, Paul
• Application Number:
  US07/651,894
• Time in Patent Office: 1,385 Days
• Field of Search: 395/800, 395/200, 395/325, 395/500, 370/85.13, 370/85.14, 370/94.1, 370/94.2, 370/60, 370/60.1, 370/85.6
• US Class Current: 710/62
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9026 Single buffer per packet
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

Claims

1. A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks in which data is carried by data packets of variable lengths, with each data packet including a header control information portion required by communication protocols used to mediate the information exchange, and a data portion for the data which is to be communicated, comprising:

a. a processor subsystem including a processor for processing the header control information portions of data packets, with the processor having access to data packets stored in a packet memory means;

b. said packet memory means is organized as a three level hierarchy comprising a first level of queue sets, each of which is comprised of a second level of linked lists of data packets, with each data packet being comprised of a third level list of buffers, said packet memory means storing data packets arriving at at least one generic adapter input/output port, with each data packet being stored in one or more of said buffers as required by the length of the data packet, with an order of use of the buffers being interchangeable;

c. a generic adapter manager means for performing and synchronizing generic adapter management functions, including implementing data structures in said packet memory means by organizing data packets in said buffers, and organizing data packets into queues for processing by said processor subsystem or transfer to or from said at least one generic adapter input/output port and processing multiple interleaved receive data streams and multiple interleaved transmit data streams; and

d. said at least one generic adapter input/output port having associated therewith a packet memory interface providing for transfer of data packets into and out of said packet memory means, such that when a data packet is received at one said generic adapter input/output port, the data packet is transferred into said packet memory means and queued for processing.

2. A generic high bandwidth adapter as claimed in claim 1, further including a generic adapter bus for connecting together said processor subsystem, said packet memory means, said generic adapter manager means, and said at least one generic adaptor input/output port.

3. A generic high bandwidth adapter as claimed in claim 2, wherein said processor subsystem further includes a first isolator for connecting the processor to said generic adapter bus, and a second isolator for connecting the processor to said generic adapter manager means.

4. A generic high bandwidth adapter as claimed in claim 2, wherein said generic adapter manager means further includes a local memory means in which the generic adapter manager means stores data structures used to organize data packets in said buffers and data packets into queues, and a local bus coupled to said generic adapter manager local memory means.

5. A generic high bandwidth adapter as claimed in claim 4, wherein said generic adapter manager means further includes a generic adapter manager kernel for implementing data structures involving said buffers, data packets and queues in said packet memory means, an arbiter for said generic adapter bus for granting bus control to a bus requester with a highest bus priority or on a round robin basis, and a monitor for said generic adapter bus for monitoring the generic adapter bus for parity checks and for checking the bus cycle length of time after bus control is granted to a bus requester.

6. A generic high bandwidth adapter as claimed in claim 2, wherein said packet memory means includes a packet memory controller for interfacing with said generic adapter bus, and for isolating the packet memory means for requirements of the generic adapter bus such as parity generation and response generation.

7. A generic high bandwidth adapter as claimed in claim 2, wherein a status notification arrangement is used to notify each said packet memory interface of the existence of data packets in at least one of the queues forming their respective transmit queue sets and comprising a status register, wherein each bit therein corresponds to a queue and indicates whether that queue is empty, with a state change of the status register being broadcast to all packet memory interfaces over said generic adapter bus.

8. A generic high bandwidth adapter as claimed in claim 2, wherein said generic adapter bus is synchronously operated.

9. A generic high bandwidth adapter as claimed in claim 1, wherein said processor subsystem further includes a processor local memory means containing communication code and code immediate control data, and a local processor subsystem bus interconnecting said processor and said processor local memory means.

10. A generic high bandwidth adapter as claimed in claim 9, wherein said processor subsystem further includes auxiliary circuits required for processor operations including hardware timers, and interrupt controller, and a local memory controller.

11. A generic high bandwidth adapter as claimed in claim 1, wherein each packet memory interface provides for obtaining said buffers from said generic adapter manager means for storing arriving data packets in said packet memory means, and also for reading out data packets from said packet memory means and passing the data packets from said packet memory means and passing the data packets to one said at least one generic adapter input/output port.

12. A generic high bandwidth adapter as claimed in claim 1, wherein each packet memory interface includes speed matching staging buffers to allow the interconnection of attachments to said at least one generic adapter input/output port having different data transmission rates.

13. A generic high bandwidth adapter as claimed n claim 1, wherein said plurality of buffer of said packet memory means include one or more pools of buffers, with each said pool comprising buffers of an identical fixed size.

14. A generic high bandwidth adapter as claimed in claim 1, wherein said generic adapter manager means organizes queues, with each queue comprising a linked list of data packets having a given priority level and destined for the same generic adapter input/output port, or to be processed in a similar manner by said processor subsystem.

15. A generic high bandwidth adapter as claimed in claim 1, wherein said generic adapter manager means defines a queue set for each generic input/output port comprising a group of queues which can be treated collectively as one operand for a given queue set operation.

16. A generic high bandwidth adapter as claimed in claim 1, wherein said packet memory means includes a plurality of queues for the processor and a plurality of output queues for the packet memory interfaces.

17. A generic high bandwidth adapter as claimed in claim 16, wherein data packets are usually discarded from output queues after they are transmitted from said packet memory means, but wherein a data packet or group of data packets can be designated as circulating, in which case said data packet or said group of data packets are not discarded but are again queued after transmission.

18. A generic high bandwidth adapter as claimed in claim 1, wherein said buffers can be linked to more than one data packet, as when attaching identical header control information portions to several data packets.

19. A generic high bandwidth adapter as claimed in claim 1, wherein the data portions of data packets can be linked to different header control information portions, without duplicating or erasing the data portions until the last data packet using a data portion is transmitted.

20. A generic high bandwidth adapter as claimed in claim 1, wherein each generic adapter input/output port includes means for examining the contents of incoming data packets and determining the proper queue to which that data packet should be enqueued.

21. A generic high bandwidth adapter as claimed in claim 20, wherein said means for examining and determining allows the generic high bandwidth adapter to be used as a multi-condition data packet switching system.

22. A generic high bandwidth adapter as claimed in claim 1, wherein a queue reconfiguration mechanism is provided to switch queuing from an original queue to an alternate queue by allocating a new base address to the original queue, such that incoming data packets are linked to the alternate queue without a requirement to notify sources of data packets, wherein the order of data packets in the queue and the order of data packets transmitted is maintained.

23. A generic high bandwidth adapter as claimed in claim 1, wherein a queue reconfiguration mechanism is provided in which each packet memory interface can take over the service of a queue by having the queue set base address of the new packet memory interface set to the set base address of the old packet memory interface, wherein the order of data packets in the queue and the order of data packets transmitted is maintained.

24. A generic high bandwidth adapter as claimed in claim 1, wherein a queue reconfiguration mechanism is provided wherein a queue may be moved in bulk to be serviced by another packet memory interface by moving the first data packet of an old queue to a new queue, wherein the order of data packets in the queue and the order of data packets transmitted is maintained.