Multi-processor system in a motor vehicle

• US 5,367,665 A
• Filed: 04/16/1992
• Issued: 11/22/1994
• Est. Priority Date: 04/16/1991
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Koch, Stefan, Buhren, Harald
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US07/869,801
• Time in Patent Office: 950 Days
• Field of Search: 371/9.1, 371/8.1, 371/68.3, 371/12, 395/575, 364/280.3, 364/280.2, 364/285.2, 364/449, 364/454
• US Class Current: 714/11
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

The invention is directed to a multi-processor system which includes at least two processors. The system carries out a first sequence of steps when power is switched on and, for a restart during operation, executes a second sequence of steps. The system distinguishes between power on and a restart and selects, the corresponding step sequence. In addition, a check is provided as to whether the number of resets of a processor has exceeded a pregiven threshold. In this case, a processor is transferred into the standby state for the operating cycle which is then running.

Claims

1. A multi-processor system for a motor vehicle for carrying out control functions, the system comprising:

at least two processors;

said processors each including means for detecting a fault of the other one of said processors during the operation of said system and means for generating a reset signal to trigger a restart of said system during the operation thereof;

means for supplying said reset signal to each of said processors at the beginning of an operating cycle when power is switched on to start said system;

said reset signal being supplied to said processors to carry out a first step sequence to define a cold start routine when power is switched on and to carry out a second step sequence to define a warm start routine when restarting said system;

each of said processors including means for distinguishing between when power is switched on and a restart based on changeable identifiers;

each of said processors having a changeable identifier which is set to a first pregiven value by said reset signal and which is set to a second pregiven value by said reset signal after said system is started;

means for permitting said processors to exchange their identifiers; and

,

each of said processors including means for comparing its own identifier to the identifier of the other processor to distinguish between when said power is switched on and a restart and for selecting the corresponding one of said step sequences.

2. The multi-processor system of claim 1, wherein said one processor is shifted into a standby state until power is switched on again.

3. The multi-processor system of claim 1, wherein each of said processors has an identifier which assumes a first value when power is switched on and which, after said first step sequence is ended, takes on a second value and which, with each restart by another processor, again assumes said first value.

4. The multi-processor system of claim 1, wherein said first step sequence is carried out when the identifier words of all processors of said system have the same value and wherein otherwise said second step sequence is carried out.

5. The multi-processor system of claim 1, wherein the value of the identifier of the processor, which is resetting the other processor, is maintained.

6. The multi-processor system of claim 1, wherein said system is used in engine controls for motor vehicles.

7. The multi-processor system of claim 1, wherein said first step sequence includes a complete check of the function of the engine control system for said motor vehicle.

8. The multi-processor system of claim 7, wherein said second step sequence is shorter than said first step sequence.

9. The multi-processor system of claim 1, further comprising means for activating an error indication when one of said processors is shifted into a standby state.

10. The multi-processor system of claim 1, wherein said processor which had been shifted into a standby state in a previous operating cycle is started in a normal manner when the power is switched on again.