Method of making charge coupled device/charge super sweep image system

• US 5,369,039 A
• Filed: 10/09/1992
• Issued: 11/29/1994
• Est. Priority Date: 11/13/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hynecek, Jaroslav
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/958,617
• Time in Patent Office: 781 Days
• Field of Search: 437/2, 437/53, 257/222
• US Class Current: 438/60
• CPC Class Codes: H01L 27/14831 Area CCD imagers
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/73 using interline transfer [IT]
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals

Abstract

Described is a new high performance CCD image sensor technology which can be used to build a versatile image senor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Claims

1. A method for fabricating an image sensor comprising:

forming a semiconductor layer of a first conductivity type;

forming a series of semiconductor wells of a second conductivity type in said semiconductor layer;

growing a first insulator layer over said semiconductor layer;

forming a semiconductor buried channel region of said first conductivity type in selected ones of said semiconductor wells;

depositing a first polysilicon layer over the first insulator layer;

depositing a patterned insulator over said first polysilicon layer above said buried channel region to define a series of charge transfer channels;

forming a series of channel stop regions adjacent respective ones of said charge transfer channels;

etching the first polysilicon layer to form a resistive gate over first portions of said buried channel region;

depositing a patterned second polysilicon layer overlying and spaced apart from said resistive gate, and overlying and spaced apart from second portions of said buried channel region; and

forming a virtual gate in said buried channel region below said resistive gate.

2. The method of claim 1 wherein said forming of said series of channel stop regions includes implanting boron in portions of said first polysilicon layer overlaying said buried channel region and not covered by said patterned insulator.

3. The method of claim 1 wherein said step of forming said virtual gate includes implanting boron.

4. The method of claim 1 wherein said first conductivity type is n type.

5. The method of claim 1 wherein said second conductivity type is p type.

6. The method of claim 1 further comprising forming said semiconductor layer over a semiconductor substrate.

7. The method of claim 6 wherein said semiconductor substrate is an epitaxial semiconductor substrate.

8. The method of claim 6 wherein said semiconductor substrate is of said first conductivity type.

9. The method of claim 8 wherein said semiconductor substrate is more heavily doped than said semiconductor layer.

10. The method of claim 1 further comprising forming a plurality of CMOS transistors in said semiconductor layer adjacent said buried channel region.