Analog-to-digital converter and method of fabrication

• US 5,369,309 A
• Filed: 10/30/1991
• Issued: 11/29/1994
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Fisher, Gregory J., Bacrania, Kantilal, Chi, Chong I.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TON, MY TRANG
• Application Number:
  US07/785,325
• Time in Patent Office: 1,126 Days
• Field of Search: 341/155, 341/156, 341/159, 341/1, 341/110, 307/260, 307/261, 328/28
• US Class Current: 327/94
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/505 with field-effect devices
• CPC Class Codes: H03G 1/0082 using bipolar transistor-type devices
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 5/15 Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors distributing, switching or gating arrangements H03K17/00
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Claims

1. A method of error correction in a two-step analog-to-digital converter, comprising the steps of:

(a) converting an input analog signal to an N-bit digital word;

(b) reconstructing a second analog signal from said N-bit word;

(c) converting an amplified difference between said input analog signal and said second signal to an M-bit word where the amplification is by a factor of 2^K ;

(d) adding to said N-bit word the two'"'"'s complement of the N-K most significant bits of the M-bit word which would result from a conversion of 0 in step (c) and thereby form a second N-bit word plus a first carry bit;

(e) adding to said second N-bit word the N-K most significant bits of said M-bit word to form a third N-bit word plus a second carry bit; and

(f) forming an output digital word with its N most significant bits equal to said third N-bit word and its M-(N-K) least significant bits equal to the M-(N-K) least significant bits of said M-bit word.

2. The method of claim 1, wherein:

(a) M equal N; and

(b) said converting of an amplified difference in step (c) is performed by the same converter as for said converting of an input analog signal in step (a).

3. The method of claim 1, further comprising the steps of:

(a) indicating an overflow or underflow when said first and second carry bits and not equal.

4. The method of claim 1, wherein:

(a) N equals 7;

(b) M equals 7;

(c) K equals 5; and

(d) said M-bit word from a conversion of 0 in step (d) equals 1000000.

5. An integrated circuit two-step analog-to-digital converter, comprising:

(a) an analog-to-digital converter (ADC) having an input and output;

(b) a digital-to-analog converter (DAC) with an input switchably coupled to either the output of said ADC or to a fixed bit pattern;

(c) an error amplifier with an input coupled to the output of said DAC and an output selectively connectable to the input of the ADC;

(d) A controller, said controller holding said error amplifier inactive for a first time interval immediately following a switching of the input of said DAC from said fixed bit pattern to said output of said ADC.

6. The converter of claim 5, further comprising:

(a) a switch selectively coupling the input of said ADC either to an output of said error amplifier or to an input sample node, and said input sample node connected to a second input of said error amplifier; and

(b) said controller switching said switch at the same time as said switching of the input of said DAC.

7. The converter of claim 6, further comprising:

(a) a sample and hold circuit with output connected to said input sample node; and

(b) said controller switching said sample and hold circuit from a hold mode to a sample mode at the same time as said error amplifier is switched into inactive and said switch is switched to connect the output of said sample and hold circuit to the input of said ADC.

8. The converter of claim 5, wherein:

(a) said error amplifier with variable gain, and during said first time interval said gain is decreased.

9. The converter of claim 5, wherein:

(a) said error amplifier during said first time interval is clamped to a 0 output.

10. A two-step analog-to-digital converter, comprising:

(a) an N-bit analog-to-digital converter (ADC) coupled to a sample terminal;

(b) an N-bit digital-to-analog converter (DAC) coupled to the output of said N-bit ADC;

(c) an error amplifier with inputs coupled to the sample terminal and an output of the DAC for amplifying the difference between a signal at said sample terminal and the output of said DAC, said amplifier amplifying by a factor of 2^K where K is less than N;

(d) an M-bit ADC coupled to an output of said error amplifier;

(e) error correction circuitry coupled to the outputs of said N-bit and M-bit ADCs and including;

(i) an adder which adds to an N-bit word output of said N-bit ADC the two'"'"'s complement of the N-K most significant bits of the M-bit word which would result from a conversion of 0 by M-bit ADC to form a second N-bit word,

(ii) a second adder which adds the N-K most significant bits of an M-bit word output of said M-bit ADC to said second N-bit word outputs by said adder,

(f) output circuitry coupled to the output of said error correction circuitry and the output of said M-bit ADC, said output circuitry concatenating an N-bit output of said second adder with the M-N+K least significant bits of an output of said M-bit ADC.

11. The converter of claim 10, further comprising:

(a) a switch coupling the input of said N-bit ADC to either said sample terminal or to said error amplifier; and

(b) said M-bit ADC is said N-bit ADC.

12. The converter of claim 11, further comprising:

(a) a sample and hold circuit at said sample terminal, the output of said sample and hold circuit connected to said error amplifier and to said switch.

13. A method of two-step analog-to-digital conversion, comprising the steps of:

(a) converting an analog input to a first digital output with a first analog-to-digital converter (ADC) while a digital-to-analog converter (DAC) has a fixed input and an error amplifier with input coupled to the output of said DAC is clamped to a fixed output;

(b) switching the input of said DAC from said fixed input to the output of said first ADC while said error amplifier remains clamped;

(c) unclamping said error amplifier after waiting a first time interval from said switching the input of said DAC;

(d) converting the output of said error amplifier with a second ADC; and

(e) combining the results of said conversions in said first ADC and second ADC.

14. The method of claim 13, further comprising the steps of:

(a) maintaining a sample and hold circuit in a hold mode while said steps of converting, switching, unclamping, and converting are performed, said sample and hold circuit with an output coupled to an input of said error amplifier; and

(b) switching said DAC to said fixed input and clamping the output of said error amplifier at the same time that said sample and hold circuit is switched into sample mode.

15. The method of claim 13, wherein:

(a) said second ADC is said first ADC.