Programmable logic device with redundant circuitry

• US 5,369,314 A
• Filed: 02/22/1994
• Issued: 11/29/1994
• Est. Priority Date: 02/22/1994
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Patel, Rakesh H., Wong, Myron W.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/199,620
• Time in Patent Office: 280 Days
• Field of Search: 307/441, 307/443, 307/465, 307/475, 307/243, 365/200, 365/230.03
• US Class Current: 326/13
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the programmable logic device. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. Programming blocks are used to program the logic array blocks and various associated logic circuitry. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programming blocks, so that the device functions identically, regardless of whether or not the redundant circuitry is used.

Claims

1. A programmable logic device comprising:

a plurality of normal logic groups each having a plurality of input terminals and a plurality of output terminals;

a plurality of sets of conductors, each set being associated with and adjacent to one of the normal logic groups, there being an equal number of normal logic groups and sets of conductors, the conductors each extending in a first dimension;

at least one redundant logic group having a plurality of input terminals and a plurality of output terminals, the normal logic groups and the redundant logic group being arrayed in a second dimension perpendicular to the first dimension; and

means associated with each set of conductors for selectively directing to each set of conductors one of;

(a) signals from the output terminals of the logic group that is associated with and adjacent to that set and (b) signals from the output terminals of another logic group that is adjacent to the set.

2. The programmable logic device defined in claim 1, wherein the logic groups each contain a region of vertical programming logic for selectively configuring the logic groups in response to vertical programming data, the programmable logic device further comprising:

a plurality of programmable switches for receiving the vertical programming data, each programmable switch being connected to a corresponding region of vertical programming logic, each programmable switch further being connected to a region of vertical programming logic in an adjacent logic group, the programmable switches further receiving and being responsive to control signals such that the vertical programming data that is received by each programmable switch is selectively directed to one of;

(a) the corresponding region of vertical programming logic and (b) the region of vertical programming logic in the adjacent logic group.

3. The programmable logic device defined in claim 2 wherein the regions of vertical programming logic each contain a plurality of registers for storing the vertical programming data.

4. The programmable logic device defined in claim 1 further comprising:

regions of horizontal programming logic for receiving horizontal programming data and for selectively configuring the logic groups in response to the horizontal programming data, the regions of horizontal programming logic being serially connected to one another, such that the horizontal programming data passes from one region of horizontal programming logic to the next, wherein the regions of horizontal programming logic further receive and are responsive to bypass signals that cause a selected region of horizontal programming logic to be bypassed.

5. The programmable logic device defined in claim 4 wherein the regions of horizontal programming logic comprise:

a plurality of registers for storing the horizontal programming data; and

means for bypassing the registers in response to the bypass signals.

6. The programmable logic device defined in claim 1 wherein the means for selectively directing comprises a plurality of programmable multiplexers for selectively directing to each set of conductors one of:

(a) the signals from the output terminals of the normal logic group that is associated with and adjacent to that set, and (b) the signals from the output terminals of another normal logic group that is adjacent to the set or the signals at the output terminals of the redundant logic group.

7. The programmable logic device defined in claim 1 further comprising control signal circuitry for receiving a plurality of stored signals and generating a corresponding plurality of control signals, the control signal circuitry having a plurality of identical subcircuits, each subcircuit comprising:

a first terminal for receiving the stored signal;

a second terminal for providing a second terminal output signal;

a third terminal for receiving the second terminal output signal of another subcircuit; and

a fourth terminal for providing one of the control signals, the second terminal output signal having a first logic level only when the stored signal is at a second logic level equal to the inverse of the first logic level and the second terminal output signal that is received at the third terminal is at the first logic level, the control signal having the second logic level only when the stored signal is at the second logic level and the output signal received at the third terminal is at the first logic level.

8. The programmable logic device defined in claim 1, wherein the logic groups each contain a plurality of macrocells, each macrocell generating an output signal that is applied to one of the output terminals.

9. The programmable logic device defined in claim 1 further comprising:

a set of horizontal input multiplexers, associated with each logic group, each horizontal input multiplexer having a plurality of horizontal multiplexer input terminals for receiving input signals and at least one horizontal multiplexer output terminal connected to one of the logic group input terminals, the horizontal input multiplexers receiving horizontal and vertical multiplexer programming data which causes each horizontal input multiplexer to selectively direct one of the input signals at a selected one of the horizontal multiplexer input terminals to the horizontal multiplexer output terminal;

a plurality of horizontal multiplexer programming blocks, each connected to one of the sets of horizontal input multiplexers for providing the horizontal multiplexer programming data to the horizontal input multiplexers; and

at least one vertical multiplexer programming block connected to a plurality of the horizontal input multiplexers for providing the vertical multiplexer programming data to the horizontal input multiplexers.

10. The programmable logic device defined in claim 9 wherein the horizontal multiplexer programming blocks contain data storage registers for storing the horizontal multiplexer programming data, wherein at least some of the horizontal multiplexer programming blocks are connected in serial and are responsive to bypass signals, and wherein when one of the horizontal multiplexer programming blocks receives one of the bypass signals that horizontal multiplexer programming block is bypassed.

11. A programmable logic device comprising:

a plurality of logic array blocks each having a plurality of data input terminals for receiving data input signals and a plurality of data output terminals, each of the logic array blocks being capable of being programmed to provide data output signals at the data output terminals that are a selected logical function of the data input signals, wherein the logic array blocks are arranged in a plurality of rows, a plurality of normal columns, and at least one redundant column;

a plurality of sets of vertical conductors, one set of vertical conductors being contained within each of the normal columns;

a plurality of sets of horizontal conductors, one set of horizontal conductors being contained within each of the rows; and

means associated with each set of vertical conductors for selectively directing to each set of vertical conductors one of;

(a) signals from the data output terminals of a logic array block that is in the same column as the set and (b) signals from the data output terminals of a logic array block that is in a column adjacent to the column containing the set.

12. The programmable logic device defined in claim 11 further comprising:

a vertical programming block in each column and each row for selectively configuring the logic array blocks in response to vertical programming data; and

a programmable switch in each normal column for directing the vertical programming data, each programmable switch being connected to a vertical programming block in the same column as the programmable switch and each programmable switch being connected to a vertical programming block in an adjacent column, the programmable switches receiving and being responsive to control signals such that the vertical programming data that is received by each programmable switch can be selectively directed to one of;

(a) a vertical programming block in the same column as the programmable switch and (b) a vertical programming block in the column adjacent to the column containing the programmable switch.

13. The programmable logic device defined in claim 12 wherein each of the vertical programming blocks contains a plurality of registers for storing the vertical programming data.

14. The programmable logic device defined in claim 11 further comprising:

a horizontal programming block in each column for selectively configuring logic array blocks in that column in response to horizontal programming data, the horizontal programming blocks being serially connected to one another, such that the horizontal programming data passes from one horizontal programming block to the next, wherein the horizontal programming blocks receive and are responsive to bypass signals, which cause a selected horizontal programming block to be bypassed.

15. The programmable logic device defined in claim 14, wherein the horizontal programming blocks comprise:

a plurality of registers for storing the horizontal programming data; and

means for bypassing the registers in response to the bypass signals.

16. The programmable logic device defined in claim 11, wherein the means for selectively directing comprises a plurality of programmable multiplexers each having a programmable multiplexer output terminal and first and second programmable multiplexer input terminals, each programmable multiplexer output terminal being coupled to one of the vertical conductors, each first multiplexer input terminal being connected to one of the data output terminals of a logic array block that is in the same column as the vertical conductor to which the programmable multiplexer output terminal is coupled, and each second multiplexer input terminal being connected to one of the data output terminals of a logic array block that is in an adjacent column.

17. The programmable logic device defined in claim 11 further comprising control signal circuitry for receiving a plurality of stored signals and generating a corresponding plurality of control signals, the control signal circuitry having a plurality of identical subcircuits, each subcircuit comprising:

a first terminal for receiving the stored signal;

a second terminal for providing a second terminal output signal;

a third terminal for receiving the second terminal output signal of another subcircuit; and

a fourth terminal for providing one of the control signals, the second terminal output signal having a first logic level only when the stored signal is at a second logic level equal to the inverse of the first logic level and the second terminal output signal that is received at the third terminal is at the first logic level, the control signal having the second logic level only when the stored signal is at the second logic level and the output signal received at the third terminal is at the first logic level.

18. The programmable logic device defined in claim 11, wherein each logic array block contains a plurality of macrocells, each macrocell generating one of the data output signals that is applied to the data output terminals.

19. The programmable logic device defined in claim 11 further comprising:

a plurality of sets of horizontal input multiplexers, each set being associated with one of the logic array blocks, each horizontal input multiplexer having a plurality of horizontal multiplexer input terminals and a horizontal multiplexer output terminal, each horizontal multiplexer output terminal being connected to one of the logic array block data input terminals, the horizontal input multiplexers receiving horizontal and vertical multiplexer programming data, each horizontal input multiplexer selectively connecting one of the horizontal multiplexer input terminals to the horizontal multiplexer output terminal in response to the vertical and horizontal multiplexer programming data;

a plurality of horizontal multiplexer programming blocks, each connected to one of the sets of horizontal input multiplexers for providing the horizontal multiplexer programming data to the horizontal input multiplexers; and

a vertical multiplexer programming block in each row connected to each of the horizontal input multiplexers in that row for providing the vertical multiplexer programming data to the horizontal input multiplexers.

20. A programmable logic device comprising:

a plurality of logic array blocks each having a plurality of data input terminals for receiving data input signals and a plurality of data output terminals, each of the logic array blocks being capable of receiving programming data for configuring the logic array block to provide data output signals at the data output terminals that are a selected logical function of the data input signals, wherein the logic array blocks are arranged in a plurality of columns, a plurality of normal rows, and at least one redundant row;

a plurality of sets of vertical conductors, each column containing one of the sets of vertical conductors;

a plurality of sets of horizontal conductors, each row containing one of the sets of horizontal conductors;

horizontal input means associated with each logic array block for selectively connecting the horizontal conductors to the data input terminals of that logic array block;

means for selectively directing the data output signals at the data output terminals of each logic array block to at least some of the horizontal conductors in the same row as that logic array block;

a set of input/output pins contained within each row; and

means for selectively connecting each set of input/output pins to the horizontal conductors in one of;

(a) the same row that contains the set of input/output pins and (b) a row adjacent to the row containing the set of input/output pins.

21. The programmable logic device defined in claim 20 further comprising:

a plurality of vertical programming blocks, each connected to one of the logic array blocks for providing the logic array blocks with vertical programming data, the vertical programming blocks in each column being connected in serial and being responsive to bypass signals so that when a row is found to contain defective circuitry the vertical programming blocks in that row are bypassed by applying the bypass signals to those vertical programming blocks.

22. The programmable logic device defined in claim 21 wherein each vertical programming block contains a plurality of serially connected data storage registers and a demultiplexer and a multiplexer, the demultiplexer and multiplexer receiving and being responsive to the bypass signals so that the data storage registers can be bypassed when the bypass signals are applied to the demultiplexer and the multiplexer.

23. The programmable logic device defined in claim 20 further comprising:

a plurality of horizontal programming blocks for providing the logic array blocks with horizontal programming data, each column containing one of the horizontal programming blocks and each horizontal programming block being connected to each of the logic array blocks in the column.

24. The programmable logic device defined in claim 23 wherein each of the horizontal programming blocks contains a plurality of data storage registers for storing the horizontal programming data.

25. The programmable logic device defined in claim 20 further comprising:

a plurality of horizontal multiplexer programming blocks, each connected to one of the horizontal input means, the horizontal multiplexer programming blocks providing the horizontal input means with horizontal multiplexer programming data, the horizontal multiplexer programming blocks in each column being serially connected and being responsive to bypass signals so that if a row is found to contain defective circuitry the horizontal multiplexer programming blocks in that row can be bypassed.

26. The programmable logic device defined in claim 25 wherein the horizontal multiplexer programming blocks each contain a plurality of serially connected data storage registers, a demultiplexer, and a multiplexer, the demultiplexer and the multiplexer receiving and being responsive to the bypass signals so that the data storage registers can be bypassed when the bypass signals are applied to the demultiplexer and the multiplexer.

27. The programmable logic device defined in claim 20 further comprising:

a plurality of vertical multiplexer programming blocks, each contained within one of the rows and being connected to each of the horizontal input means in the row for providing the horizontal input means with vertical multiplexer programming data, the vertical multiplexer programming blocks being serially connected and being responsive to bypass signals so that if a row is found to contain defective circuitry the vertical multiplexer programming block in that row can be bypassed.

28. The programmable logic device defined in claim 27 wherein each of the vertical multiplexer programming blocks contains a plurality of serially connected data storage registers, a demultiplexer, and a multiplexer, the demultiplexer and the multiplexer receiving and being responsive to the bypass signals so that the data storage registers can be bypassed when the bypass signals are applied to the demultiplexer and multiplexer.

29. The programmable logic device defined in claim 20 wherein each horizontal input means comprises a plurality of horizontal input multiplexers, each horizontal input multiplexer having a plurality of horizontal input multiplexer input terminals connected to some of the horizontal conductors and a horizontal input multiplexer output terminal connected to one of the input terminals of one of the logic array blocks.

30. The programmable logic device defined in claim 20 wherein each of the logic array blocks contains a plurality of macrocells, each macrocell generating one of the data output signals applied to the output terminals.

31. The programmable logic device defined in claim 20 further comprising:

a plurality of vertical input/output programming blocks connected to the means for selectively connecting, each row containing one of the vertical input/output programming blocks for providing vertical input/output programming data to program the means for selectively connecting; and

a horizontal input/output programming block connected to the means for selectively connecting for providing horizontal input/output programming data to program the means for selectively connecting.