Sinewave generating circuit and amplitude demodulator

• US 5,369,375 A
• Filed: 02/26/1993
• Issued: 11/29/1994
• Est. Priority Date: 01/11/1989
• Status: Expired due to Term

• Current Assignee: Uusi LLC (Nartron Corporation)
• Original Assignee: Nartron Corporation
• Inventors: Findikli, Nadi S., Shank, David W., Munch, Carl A., Cooper, Stephen R. W.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/023,400
• Time in Patent Office: 641 Days
• Field of Search: 329/347, 328/14, 324/207.16, 324/207.17, 324/207.18, 340/870.3, 340/870.31, 340/870.32
• US Class Current: 329/347
• CPC Class Codes: B60G 17/01933 Velocity, e.g. relative velocity-displacement sensors
• CPC Class Codes: B60G 2204/111 on pneumatic springs
• CPC Class Codes: B60G 2204/112 on dampers, e.g. fluid dampers
• CPC Class Codes: B60G 2400/202 Piston speed; Relative velocity between vehicle body and wheel
• CPC Class Codes: B60G 2400/25 Stroke; Height; Displacement
• CPC Class Codes: B60G 2400/252 vertical
• CPC Class Codes: B60G 2401/17 Magnetic/Electromagnetic
• CPC Class Codes: G01D 5/2046 by a movable ferromagnetic element, e.g. a core
• CPC Class Codes: G01D 5/2053 by a movable non-ferromagnetic conductive element

Abstract

An integrated circuit for driving a sensor includes an oscillator for providing a first clock signal synchronized to a periodic waveform supplied by an external source. A second clock signal in the form of a uni-polar square wave is derived from the first clock signal. A sinewave signal is generated by consecutively selecting voltage steps from a resistor ladder under control of the second clock signal. A low-pass filter removes from the sinewave signal higher frequency harmonics generated by switching through the steps of the resistor ladder. A linear amplifier utilizes an external capacitor to couple the filtered sinewave signal to the sensor. Temperature compensation is provided by comparing the voltage of the sinewave signal supplied to the sensor with an external temperature stable reference voltage. The integrated circuit also includes circuitry for amplitude demodulating a signal returned from the sensor to provide a sensor output signal.

Claims

1. Apparatus for generating a low-distortion sinewave and amplitude demodulating an input time-varying signal derived from the generated sinewave or an external source and producing an output proportional to the amplitude demodulated signal with said apparatus comprising:

a) activation circuitry for generating and driving a low-distortion sinewave with said activation circuitry including an oscillator first means, a second means for selecting frequency and a third means driving the sinewave with an amplitude that is proportional to an input reference level; and

b) monitoring circuity coupleable to said time-varying signal to achieve said amplitude demodulation including a means to detect the amplitude of the time-varying signal and a second means to provide a signal proportional to the amplitude with an adjustable scale of proportion.

2. The apparatus of claim 1 wherein said apparatus is incorporated in an integrated circuit where said means to detect the amplitude consists of an amplitude detector and said sinewave generation is accomplished via a resistor divider network and filter comprising:

a) a gating means to generate a first clock signal from said oscillator means;

b) a reference voltage first means applied across said resistor divider network with a second switching means to individually couple the signal at each resistor to the divider network output and a third means consisting of selected values for the resistors to limit departure from sinusoidal time variation in the resistor network divider output;

c) a gating and timing means to sequentially activate the switching means and thereby sequentially connect the signal at each resistor of the divider to the network divider output, at and for specific time intervals with said timing intervals derived from the clock signal and selected to limit departure from sinusoidal time variation in the resistor network divider output;

d) a frequency selection means to control the rate at which the divider network is switched;

e) filter means placed in series with the network divider output to remove distortion from the network divider output and thereby produce a desired approximation to sinusoidal output; and

f) linear amplifier means to drive the filter output at a power level higher than that produced by the resistor divider and filter network.

3. The apparatus of claim 2 wherein said resistor network consists of a multiplicity of discrete values which are switched sequentially between the lowest and highest divider voltage to achieve near sinusoidal variation.

4. The apparatus of claim 2 where said resistor network consists of 16 discrete values which are switched sequentially between the lowest and highest divider voltage to achieve near sinusoidal variation.

5. The apparatus of claim 2 where said reference voltage is varied by gain control means to keep the output sinewave voltage amplitude proportional to an external reference voltage.

6. The apparatus of claim 5 where gain control consists of a first output sinewave amplitude detection means, a second comparison means to compare said sinewave amplitude to said external reference and a third control means to increase or decrease said voltage divider reference if said sinewave amplitude is above or below said reference voltage.

7. The apparatus of claim 6 where said amplitude detection means consists of a delta modulator detector means.

8. The apparatus of claim 6 where said amplitude detection means consists of a diode rectifier followed by a low-pass filter means.

9. The apparatus of claim 6 where said amplitude detection means consists of a diode rectifier placed in the feedback loop of an operational amplifier means.

10. The apparatus of claim 6 where said amplitude detection means consists of a sine mixer means.

11. The apparatus of claim 6 where said amplitude detection means consists of a peak detector means.

12. The apparatus of claim 11 where said peak detector means consists of a track and hold peak detector means.

13. The apparatus of claim 2 where said amplitude detector consists of a peak detector means.

14. The apparatus of claim 2 where said amplitude detector consists of a track and hold peak detector.

15. The apparatus of claim 2 where said amplitude detector consists of a diode rectifier followed by a low-pass filter.

16. The apparatus of claim 2 where said amplitude detector consists of a diode rectifier placed in the feedback loop of an operational amplifier means.

17. The apparatus of claim 2 where said amplitude detector consists of a delta modulator detector.

18. The apparatus of claim 2 where said amplitude detector consists of a sine mixer means.

19. The apparatus of claim 18 where a sinewave signal used in said sine mixer means is derived from the output of said sinewave generation means.

20. The apparatus of claim 2 where said amplitude detector is preceded by or incorporates an amplifier means.

21. The apparatus of claim 20 where said amplifier and amplitude detector present at least 50 KΩ

of impedance at the detector input to the apparatus.

22. The apparatus of claim 14 where said peak detector consists of two time-multiplexed track and hold peak detectors followed by a filter means to eliminate switching noise.

23. The apparatus of claim 2 where said linear amplifier means consists of a negative feedback amplifier circuit.

24. The apparatus of claim 23 where said negative feedback amplifier circuit consists of an operational amplifier incorporated in the integrated circuit and having the non-inverting, inverting and output lines pin accessible.

25. The apparatus of claim 2 where said frequency selection means consists of a divide-down counter to divide down from the first clock signal and thereby generate a second lower frequency clock signal from among a multiplicity of pin selectable divide-down ratios.

26. The apparatus of claim 25 wherein said divide-down counter provides eight possible frequencies via three pins that are programmed via "pull-up" resistors or leads to a reference voltage logic level or "pull-down" resistors or leads to ground.