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Method for optimum erasing of EEPROM

  • US 5,369,615 A
  • Filed: 11/08/1993
  • Issued: 11/29/1994
  • Est. Priority Date: 03/15/1991
  • Status: Expired due to Term
First Claim
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1. For an array of a plurality of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor that includes a floating gate and an erase electrode, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array, comprising the steps of:

  • reading a first set of erase parameters previously stored in said sector;

    erasing said sector by using said first set of erase parameters;

    determining a second set of erase parameter for optimally erasing of said sector in a subsequently erase; and

    storing back said second set of erase parameters in said sector.

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