Method for optimum erasing of EEPROM

• US 5,369,615 A
• Filed: 11/08/1993
• Issued: 11/29/1994
• Est. Priority Date: 03/15/1991
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Gross, Stephen J., Harari, Eliyahou, Mehrotra, Sanjay, Guterman, Daniel C.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/149,602
• Time in Patent Office: 386 Days
• Field of Search: 365/218, 365/189.01, 365/185, 365/230.03
• US Class Current: 365/185.19
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single- and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group, Defects handling includes an adaptive data encoding scheme.

Claims

1. For an array of a plurality of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor that includes a floating gate and an erase electrode, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array, comprising the steps of:

reading a first set of erase parameters previously stored in said sector;

erasing said sector by using said first set of erase parameters;

determining a second set of erase parameter for optimally erasing of said sector in a subsequently erase; and

storing back said second set of erase parameters in said sector.

2. The method as in claim 1, wherein said set of erase parameters includes a first initial erase voltage, and the step of erasing said sector includes pulsing said sector with an incremental erase voltage beginning from substantially said first initial erase voltage until said sector is erased.

3. The method as in claim 2, wherein the second set of erase parameter includes a second initial erase voltage that is substantially equal to the incremented erase voltage when the sector is erased.

4. For an array of a plurality of electrically erasable and programmable read only memory cells, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein and capable of undergoing a plurality of program and erase cycles, a method of erasing a sector of addressed cells of the array, comprising the steps of:

reading a first set of erase parameters previously stored in said sector;

erasing said sector by using said first set of erase parameters;

determining a second set of erase parameter for optimally erasing of said sector in a subsequently erase; and

storing back said second set of erase parameters in said sector.

5. The method as in claim 4, wherein said first set of erase parameters includes a first initial erase voltage usable to establish a starting erase voltage for the erasing of said sector.

6. The method as in claim 4, further including the step of:

providing a lookup table of optimum erase parameters for a range of sectors which have undergone different program/erase cyclings; and

wherein;

said first set of erase parameters includes a first number of program/erase cycles (or "cycle count") a sector has undergone as the sector is being program/erase cycled during use of the memory array;

the step of erasing said sector includes looking up the optimum erase parameters from the lookup table for that first cycle count; and

said second set of erase parameter includes a second cycle count that is incremented from said first cycle count by one.