Method for optimum erasing of EEPROM
First Claim
1. For an array of a plurality of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor that includes a floating gate and an erase electrode, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array, comprising the steps of:
- reading a first set of erase parameters previously stored in said sector;
erasing said sector by using said first set of erase parameters;
determining a second set of erase parameter for optimally erasing of said sector in a subsequently erase; and
storing back said second set of erase parameters in said sector.
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Accused Products
Abstract
Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single- and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group, Defects handling includes an adaptive data encoding scheme.
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Citations
6 Claims
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1. For an array of a plurality of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor that includes a floating gate and an erase electrode, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array, comprising the steps of:
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reading a first set of erase parameters previously stored in said sector; erasing said sector by using said first set of erase parameters; determining a second set of erase parameter for optimally erasing of said sector in a subsequently erase; and storing back said second set of erase parameters in said sector. - View Dependent Claims (2, 3)
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4. For an array of a plurality of electrically erasable and programmable read only memory cells, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein and capable of undergoing a plurality of program and erase cycles, a method of erasing a sector of addressed cells of the array, comprising the steps of:
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reading a first set of erase parameters previously stored in said sector; erasing said sector by using said first set of erase parameters; determining a second set of erase parameter for optimally erasing of said sector in a subsequently erase; and storing back said second set of erase parameters in said sector. - View Dependent Claims (5, 6)
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Specification