Method for assuring that an erase process for a memory array has been properly completed

• US 5,369,616 A
• Filed: 03/07/1994
• Issued: 11/29/1994
• Est. Priority Date: 10/30/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E., Magnusson, Eric J.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/207,228
• Time in Patent Office: 267 Days
• Field of Search: 365/218, 365/900, 365/201, 371/21.6
• US Class Current: 365/185.22
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.

Claims

1. A method for insuring that each erase operation practiced on a block of flash EEPROM transistors which is part of a flash EEPROM memory array is carried out reliably, each flash EEPROM transistor storing a bit having a first state and a second state, each erase operation bringing the bits in the block to the first state, the method comprising the steps of:

designating a first group of three bits in the block to represent the condition of erase operations;

b) programming to the second state a first bit of the first group of three bits to indicate that an erase operation should take place on the block;

c) programming to the second state a second bit of the first group of three bits before an erase operation begins;

d) beginning a first erase operation, completion of the first erase operation bringing all bits of the first group of three bits to the first state;

e) if the first erase operation was successfully completed programming to the second state a third bit of the first group of three bits;

f) testing all bits of the first group of three bits to determine their condition in response to the reapplication of power to the flash EEPROM array; and

g) initiating a second erase operation unless the third bit of the first group of three bits is in the second state and the first and the second bit of the three bits both are in the first state.

2. The method of claim 1 in which the step of programming to the second state the second bit of the three bits comprises applying programming signals to the second bit of the first group of three bits a plurality of times such that the second bit of the first group of three bits becomes more difficult to erase.

3. The method of claim 1 wherein step a) includes designating a second group of three bits in the block to represent the condition of erase operations and wherein steps b)-f) are also performed on the second group of three bits.

4. The method of claim 2 wherein step a) includes designating a second group of three bits in the block to represent the condition of erase operations and wherein steps b)-f) are also performed on the second group of three bits.