High speed memory interface for video teleconferencing applications

• US 5,369,617 A
• Filed: 12/21/1993
• Issued: 11/29/1994
• Est. Priority Date: 12/21/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Munson, Bill A.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/172,113
• Time in Patent Office: 343 Days
• Field of Search: 365/189.01, 365/189.04, 365/230.01, 365/230.03, 365/230.08, 365/219
• US Class Current: 365/219
• CPC Class Codes: H04N 7/148 Interfacing a video terminal to a particular transmission medium, e.g. ISDN
• CPC Class Codes: H04N 7/152 Multipoint control units therefor

Abstract

A high speed memory interface, contained within a video teleconferencing system, couples a capture first-in first-out (FIFO) device, a host FIFO, a PB FIFO, and a display FIFO to a high speed memory. The interface includes a high speed channel interface, including an arbiter, that allocates bandwidth for the high speed memory for a display service, a capture service, a host service and a refresh service. The capture FIFO receives raw capture video data, buffers the raw capture video data at a capture rate, and transfers the raw capture video data to the high speed memory. The host FIFO receives display video data from a remote source, buffers the display video data, and transfers the input display video data to the high speed memory. The PB FIFO reads capture video data and display video data, during the PB service, from the high speed memory to provide an input queue for video compression and video decompression. The display FIFO receives, during the display service, display video data from the high speed memory, and buffers the display video data to provide the display video data at a display rate for the host. The high speed memory interface has application for use in a computer system supporting video teleconferencing.

Claims

1. An apparatus for interfacing a high speed memory for video teleconferencing between a host and at least one a remote source, said apparatus comprising:

a high speed channel interface including an arbiter, coupled to said high speed memory, for allocating bandwidth for said high speed memory for display service, capture service, host service and refresh service;

a capture FIFO, including capture transfer logic, coupled to said high speed channel interface, for receiving raw capture video data, and for buffering said raw capture video data at a capture rate, and for transferring said raw capture video data from said capture FIFO to said high speed memory during said capture service;

a host FIFO, including host transfer logic, coupled to said high speed channel interface, for receiving input display video data from said at least one remote source, for buffering said input display video data, and said host transfer logic for transferring said input display video data from said host FIFO, during said host service, to said high speed memory, and for transferring, from said high speed memory, capture video data, during said host service, to said host FIFO; and

a display FIFO, including display transfer logic, coupled to said high speed channel interface, for transferring display video data, during said display service, from said high speed memory to said display FIFO, and for buffering said display video data to provide said display video data at a display rate for said host.

2. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 1, wherein said high speed memory delivers, and said high speed channel interface transfers data up to 500 Megabytes per second.

3. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 1, wherein:

said bus arbiter being capable of allocating bandwidth of said high speed memory for PB service; and

a pixel processing interface, including a PB FIFO and PB transfer logic, coupled to said high speed channel interface, for transferring said capture video data, during said PB service, from said high speed memory to said PB FIFO to provide an input queue for video compression, said PB transfer logic being capable of transferring said display video data, during said PB service, from said high speed memory to said PB FIFO to provide an input queue for video decompression.

4. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 3, wherein said arbiter comprises a static priority arbiter for assigning a first priority to said display service, a second priority for said refresh service, a third priority to said capture service, a fourth priority to said host service, and a fifth priority to said PB service.

5. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 1, wherein said host FIFO comprises an ISA bus interface to interface said host FIFO to an ISA bus, said host FIFO comprising a size capable of supporting a maximum latency requirement for said ISA bus.

6. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 1, wherein said display transfer logic comprises capture video display logic for transferring raw capture video data, during said display service, from said high speed memory to said display FIFO, to provide said raw capture video data at a capture display rate for said host.

7. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 1, wherein said capture rate comprises 60 Hz per field, and said display rate comprises a vertical refresh rate of 70 Hz.

8. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 1, wherein:

said raw capture video data comprises CCIR 601 (YUV

     16) video data;

said capture FIFO comprises;

a Y FIFO for buffering said Y capture video data;

a U FIFO for buffering said U capture video data; and

a V FIFO for buffering said V capture video data;

said display video data comprises YUV 16 display video data; and

said display FIFO comprises;

a Y display FIFO for buffering said Y display video data;

a U display FIFO for buffering said display video data; and

a V display FIFO for buffering said V display video data.

9. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 8, wherein said arbiter comprises a mechanism for allocating bandwidth for said high speed memory for display service in evenly spaced intervals for said Y display FIFO, U display FIFO, and V display FIFO, and said arbiter comprises a mechanism for allocating bandwidth for said high speed memory for capture service in evenly spaced intervals for said Y capture FIFO, U capture FIFO, and V capture FIFO.

10. An apparatus for interfacing a high speed memory for video teleconferencing between a host and at least one a remote source, said apparatus comprising:

high speed memory interface means, coupled to said high speed memory, including arbitration means for allocating bandwidth for said high speed memory for display service, capture service, host service and refresh service;

capture means, coupled to said high speed memory interface means, for capturing video data for receiving raw capture video data, said capture means including capture buffer means for buffering said raw capture video data at a capture rate, and for transferring said raw capture video data from said capture buffer means to said high speed memory during said capture service;

host interface means including host buffer means, coupled to said high speed memory interface means, for receiving input display video data from said at least one remote source, for buffering said input display video data in said host buffer means, and for transferring said input display video data from said host buffer means, during said host service, to said high speed memory, and for transferring, from said high speed memory, capture video data, during said host service, to said host buffer means; and

display means coupled to said high speed memory interface means for transferring display video data, during said display service, from said high speed memory to a display buffer, and said display means including display buffer means for buffering said display video data to provide said display video data at a display rate for said host.

11. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 10, wherein said high speed memory comprises a RDRAM™

, and said high speed memory interface means comprises a Rambus™

channel interface.

12. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 10, wherein:

said arbitration means is capable of allocating bandwidth of said high speed memory for PB service; and

pixel processing interface means, including PB buffer means, coupled to said bus arbitration means, for interfacing a pixel processing unit to said high speed memory, said pixel processing interface means being capable of transferring said capture video data, during said PB service, from said high speed memory to said PB buffer means to provide an input queue for video compression, said pixel processing interface means capable of transferring said display video data, during said PB service, from said high speed memory to said PB buffer means to provide an input queue for video decompression.

13. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 12, wherein said arbitration means comprises static priority means for allocating said high speed memory bandwidth by assigning a first priority to said display service, a second priority for said refresh service, a third priority to said capture service, a fourth priority to said host service, and a fifth priority to said PB service.

14. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 10, wherein said host interface means comprises an ISA interface means for interfacing said host interface means to an ISA bus, said ISA interface means being capable of supporting a maximum latency requirement for said ISA bus.

15. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 10, wherein said display means comprises capture video data display means for transferring raw capture video data, during said display service, from said high speed memory to said display buffer, and said display buffer means for buffering said raw capture video data to provide said raw capture video data at a display rate for said host.

16. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 10, wherein said capture rate comprises 60 Hz per field, and said display rate comprises a vertical refresh rate of 70 Hz.

17. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 10, wherein:

said raw capture video data comprises CCIR 601 (YUV

     16) video data;

said capture buffer means comprises;

Y capture buffer means for storing said Y capture video data;

U capture buffer means for storing said U capture video data; and

V capture buffer means for storing said V capture video data;

said display video data comprises YUV 16 display video data; and

said display buffer means comprises;

Y display buffer means for storing said Y display video data;

U display buffer means for storing said U display video data; and

V display buffer means for storing said V display video data.

18. The apparatus for interfacing a high speed memory for video teleconferencing as set forth in claim 17, wherein said arbitration means is capable of allocating bandwidth for said high speed memory for display service in evenly spaced intervals for said Y display buffer means, U display buffer means, and V display buffer means, and said arbitration means is capable of allocating bandwidth for said high speed memory for capture service in evenly spaced intervals for said Y capture buffer means, U capture buffer means, and V capture buffer means.

19. A method for interfacing a high speed memory for video teleconferencing between a host and at least one a remote source, said method comprising the steps of:

allocating bandwidth for said high speed memory for display service, capture service, host service and refresh service;

receiving input display video data from said at least one remote source;

buffering said input display video data in a host buffer;

transferring said input display video data from said host buffer, during said host service, to said high speed memory;

receiving raw capture video data from a video source;

buffering said raw capture video data in a capture buffer at a capture rate;

transferring said raw capture video data from said capture buffer to said high speed memory during said capture service;

transferring, from said high speed memory, capture video data, during said host service, to said host buffer for buffering in said host buffer;

transferring display video data, during said display service, from said high speed memory to a display buffer; and

buffering said display video data in said display buffer so as to provide said display video data at a display rate for said host.

20. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 19, wherein said high speed memory delivers, and said high speed channel interface transfers data up to 500 Megabytes per second.

21. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 19, further comprising the steps of:

allocating bandwidth of said high speed memory for PB service;

transferring said capture video data, during said PB service, from said high speed memory to a PB buffer;

buffering, in said PB buffer, said capture video data to provide an input queue for video compression;

transferring said display video data, during said PB service, from said high speed memory to a PB buffer; and

buffering, in said PB buffer, said display video data to provide an input queue for video decompression.

22. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 21, wherein the step of allocating bandwidth for said high speed memory comprises the steps of:

assigning a first priority to said display service;

assigning a second priority for said refresh service;

assigning a third priority to said capture service;

assigning a fourth priority to said host service; and

assigning a fifth priority to said PB service.

23. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 19, wherein said step of buffering said display video data and said capture video data in said host buffer supports a maximum latency requirement for said industry standard (ISA) bus.

24. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 19, further comprising the steps of:

transferring raw capture video data, during said display service, from said high speed memory to said display buffer; and

buffering said raw capture video data in said display buffer so as to provide said raw capture video data at a display rate for said host.

25. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 19, wherein:

the step of buffering said raw capture video comprises the step of buffering said raw capture video at a capture rate of 60 Hz per field; and

the step of buffering said display video data comprises the step of buffering said display video data at a vertical refresh rate of 70 Hz.

26. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 19, wherein:

the step of receiving raw capture video data comprises the step of receiving CCIR 601 (YUV

     16) video data;

the step of buffering said raw capture video data comprises the steps of;

storing said Y capture video data in a Y capture first-in first-out (FIFO) memory;

storing said U capture video data in a U capture FIFO memory; and

storing said V capture video data in a Y capture FIFO memory;

the step of transferring display video data comprises the step of transferring YUV 16 display video data; and

the step of buffering said display video data in said display buffer comprises the steps of;

storing said Y display video data in a Y display FIFO memory;

storing said U display video data in a U display FIFO memory; and

storing said V display video data in a Y display FIFO memory.

27. The method for interfacing a high speed memory for video teleconferencing as set forth in claim 26, wherein:

the step of allocating bandwidth for said high speed memory for display service comprises the step of servicing said Y display FIFO, U display FIFO, and V display FIFO in evenly spaced intervals; and

the step of allocating bandwidth for said high speed memory for capture service comprises the step of servicing said Y capture FIFO, U capture FIFO, and V capture FIFO in evenly spaced intervals.

28. A computer system comprising:

a central processing unit (CPU);

memory coupled to said CPU;

a bus coupled to said CPU;

an output display, coupled to said bus, for displaying graphics and video;

a remote interface coupled to said bus, for interfacing said computer system to at least one remote source;

a graphics subsystem, coupled to said bus, for generating graphics, including an encoded key, for display on said output display;

a video teleconferencing subsystem, coupled to said bus for teleconferencing between said computer system and said at least one remote source, said video teleconferencing subsystem comprising;

a host interface coupled to said bus to interface said video teleconferencing subsystem;

a capture unit for capturing video data in said computer system;

a display unit for generating display video data for display on said output display;

an image processing unit for compressing and decompressing video data;

a high speed memory for storing capture video data and display video data;

a high speed memory interface, coupling said capture unit, said image processing unit, and said display unit to said high speed memory; and

a chroma key circuit, coupling said graphics subsystem and said video teleconferencing subsystem to said output display, for coupling said video to said output display when said chroma keying circuit detects said encoded key in said graphics, and for coupling said graphics to said output display when said chroma keying circuit does not detect said encoded key in said graphics.

29. The computer system as set forth in claim 28, wherein said high speed memory interface comprises:

a high speed channel interface including an arbiter, coupled to said high speed memory, for allocating bandwidth for said high speed memory for display service, capture service, host service, refresh service and PB service;

a capture FIFO, including capture transfer logic, coupled to said high speed channel interface and said capture unit, for receiving raw capture video data, and for buffering said raw capture video data at a capture rate, and said capture transfer logic transferring said raw capture video data from said capture FIFO to said high speed memory during said capture service;

a host FIFO, including host transfer logic, coupled to said high speed channel interface and said host interface unit, for receiving input display video data via said bus, for buffering said input display video data, and said host transfer logic being capable of transferring said input display video data from said host FIFO, during said host service, to said high speed memory, and for transferring, from said high speed memory, capture video data, during said host service, to said host FIFO;

a display FIFO, including display transfer logic, coupled to said high speed channel interface and said display unit, for transferring display video data, during said display service, from said high speed memory to said display FIFO, and for buffering said display video data to provide said display video data at a display rate for said host; and

a pixel processing interface, including a PB FIFO and PB transfer logic, coupled to said high speed channel interface and said image processing unit, for transferring said capture video data, during said PB service, from said high speed memory to said PB FIFO to provide an input queue for video compression, for transferring said display video data, during said PB service, from said high speed memory to said PB FIFO to provide an input queue for video decompression.

30. The computer system as set forth in claim 29, wherein said high speed memory delivers, and said high speed channel interface transfers data up to 500 Megabytes per second.

31. The computer system as set forth in claim 29, wherein said arbiter comprises a static priority arbiter for assigning a first priority to said display service, a second priority for said refresh service, a third priority to said capture service, a fourth priority to said host service, and a fifth priority to said PB service.

32. The computer system as set forth in claim 29, wherein:

said bus comprises an ISA bus; and

said host FIFO comprises an ISA bus interface for interfacing said host FIFO to said ISA bus, said host FIFO comprising a sufficient number of entries to support a maximum latency requirement for said ISA bus.

33. The computer system as set forth in claim 29, wherein said display transfer logic comprises capture video display logic for transferring raw capture video data, during said display service, from said high speed memory to said display FIFO to provide said raw capture video data at a capture display rate for display on said output display.

34. The computer system as set forth in claim 29, wherein said capture rate comprises 60 Hz per field, and said display rate comprises a vertical refresh rate of 70 Hz.

35. The computer system as set forth in claim 29, wherein:

said raw capture video data comprises CCIR 601 (YUV

     16) video data;

said capture FIFO comprises;

a Y FIFO for buffering said Y capture video data;

a U FIFO for buffering said U capture video data; and

a V FIFO for buffering said V capture video data;

said display video data comprises YUV 16 display video data; and

said display FIFO comprises;

a Y display FIFO for buffering said display video data;

a U display FIFO for buffering said U display video data; and

a V display FIFO for buffering said V display video data.

36. The computer system as set forth in claim 29, wherein said arbiter is capable of allocating bandwidth for said high speed memory, during display service, in evenly spaced intervals for said Y display FIFO, U display FIFO, and V display FIFO, and said arbiter is capable of allocating bandwidth for said high speed memory for capture service in evenly spaced intervals for said Y capture FIFO, U capture FIFO, and V capture FIFO.