Semiconductor memory device reading/writing data of multiple bits internally

• US 5,369,619 A
• Filed: 10/22/1991
• Issued: 11/29/1994
• Est. Priority Date: 10/24/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ohba, Atsushi
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/780,582
• Time in Patent Office: 1,134 Days
• Field of Search: 365/230.03, 365/230.06, 365/230.01, 365/238.5, 365/63
• US Class Current: 365/230.03
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device includes a memory cell array divided into a plurality of block. In one region on the memory chip, four blocks, two input/output circuits, and two data buses are arranged. In the other region on the chip, four blocks, two input/output circuits, and two data buses are arranged. Each block in each region is divided into two sub-blocks corresponding to the two input/output circuits. Each data bus is connected between the corresponding input/output circuit in the same region and the corresponding two sub-blocks.

Claims

1. A semiconductor memory device in which reading/writing operation of data of a plurality of bits is carried out internally, said semiconductor memory device being substantially rectangular with a length in a first direction and a width in a second direction, at right angles with said first direction, and including a first region and a second region arranged along said first direction, comprising:

a first set of a plurality of memory array blocks provided in said first region and being arranged in first and second rows along said first direction, each memory array blocks comprising one or more sub-blocks,

a second set of a plurality of memory array blocks provided in said second region and being arranged in first and second rows along said first direction, each memory array blocks comprising one or more sub-blocks,

a first set of one or more input/output means provided in said first region, for input/output of data of a plurality of bits, and connected to said one or more sub-blocks included in each of said first set of a plurality of memory array blocks in the first region,

a second set of one or more input/output means provided in said second region for input/output of data of a plurality of bits and connected to said one or more sub-blocks included in each of said second set of a plurality of memory array blocks in the second region,

a first set of one or more data buses provided in said first region, each of said first set of one or more data buses being connected between the corresponding input/output means in said first region and the corresponding sub-blocks in said first region,

a second set of one or more data buses provided in said second region, each of said second set of one or more data buses being connected between the corresponding input/output means in said second region and the corresponding sub-blocks in said second region,

block selecting means for selecting simultaneously one of said plurality of memory array blocks in each of said first and second regions for reading/writing of said data of a plurality of bits, and being arranged along said first direction at one side of said first and second rows of the plurality of memory array blocks,

a first set of a plurality of main word lines extending along said first direction in said first row of memory array blocks, each main word line commonly provided to said first row of memory array blocks of each region,

a second set of a plurality of main word lines extending along said first direction in said second row of memory array blocks, each main word line commonly provided to said second row of memory array blocks of each region,

first main word line selecting means for selecting one of said first set of main word lines and being arranged along said second direction and positioned between said first and second regions, and

second main word line selecting means for selecting one of said second set of main word lines and being arranged along said second direction and positioned between said first and second regions.

2. A semiconductor memory device in which reading/writing operation of data of a plurality of bits is carried out internally, said semiconductor memory device being substantially rectangular with a length in a first direction and a width in a second direction, at right angles with said first direction, and including a first region and a second region arranged along said first direction, comprising:

a first set of a plurality of memory array blocks provided in said first region and being arranged in first and second rows along said first direction, each memory array blocks comprising one or more sub-blocks,

a second set of a plurality of memory array blocks provided in said second region and being arranged in first and second rows along said first direction, each memory array blocks comprising one or more sub-blocks,

a first set of one or more input/output means provided in said first region, for input/output of data of a plurality of bits, and connected to said one or more sub-blocks included in each of said first set of a plurality of memory array blocks in the first region,

a second set of one or more input/output means provided in said second region for input/output of data of a plurality of bits and connected to said one or more sub-blocks included in each of said second set of a plurality of memory array blocks in the second region,

a first set of one or more data buses provided in said first region, each of said first set of one or more data buses being connected between the corresponding input/output means in said first region and the corresponding sub-blocks in said first region,

a second set of one or more data buses provided in said second region, each of said second set of one or more data buses being connected between the corresponding input/output means in said second region and the corresponding sub-blocks in said second region,

block selecting means for selecting simultaneously one of said plurality of memory array blocks in each of said first and second regions for reading/writing of said data of a plurality of bits,

a first set of a plurality of main word lines extending along said first direction in said first row of memory array blocks, each main word line commonly provided to said first row of memory array blocks of each region,

a second set of a plurality of main word lines extending along said first direction in said second row of memory array blocks, each main word line commonly provided to said second row of memory array blocks of each region, and

main word line selecting means for selecting one of said first set of main word lines and one of said second set of main word lines, wherein

said main word line selecting means and said block selecting means are arranged along said second direction and positioned between said first and second regions.

3. A semiconductor memory device in which reading/writing operation of data of a plurality of bits is carried out internally, said semiconductor memory device being substantially rectangular with a length in a first direction and a width in a second direction, at right angles with said first direction, and including a first region and a second region arranged along said first direction, comprising:

a first set of a plurality of memory array blocks provided in said first region and being arranged in first and second rows along said first direction, each memory array block comprising one or more sub-blocks,

a second set of a plurality of memory array blocks provided in said second region and being arranged in first and second rows along said first direction, each memory array block comprising one or more sub-blocks,

a first set of one or more input/output means provided in said first region, for input/output of data of a plurality of bits, and connected to said one or more sub-blocks included in each of said first set of a plurality of memory array blocks in the first region,

a second set of one or more input/output means provided in said second region for input/output of data of a plurality of bits and connected to said one or more sub-blocks included in each of said second set of a plurality of memory array blocks in the second region,

a first set of one or more data buses provided in said first region, each of said first set of one or more data buses being connected between the corresponding input/output means in said first region and the corresponding sub-blocks in said first region,

a second set of one or more data buses provided in said second region, each of said second set of one or more data buses being connected between the corresponding input/output means in said second region and the corresponding sub-blocks in said second region,

block selecting means for selecting simultaneously one of said plurality of memory array blocks in each of said first and second regions for reading/writing of said data of a plurality of bits,

a first set of a plurality of main word lines extending along said first direction in said first row of memory array blocks, each main word line commonly provided to said first row of memory array blocks of each region,

a second set of a plurality of main word lines extending along said first direction in said second row of memory array blocks, each main word line commonly provided to said second row of memory array blocks of each region,

main word line selecting means for selecting one of said first set of main word lines and one of said second set of main word lines, and

a plurality of block selecting lines for transmitting an output from said block selecting means to said plurality of memory array blocks provided in said first region and in said second region, wherein

said main word line selecting means and said block selecting means are arranged along said second direction and positioned between said first and second regions, and

each block selecting line is connected between one of said plurality of memory array blocks provided in said first region and one of said plurality of memory array blocks provided in said second region through said block selecting means, so that the length of each of said plurality of block selecting lines are nearly equal to each other.