Built-in self-test circuit

• US 5,369,648 A
• Filed: 11/08/1991
• Issued: 11/29/1994
• Est. Priority Date: 11/08/1991
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: NCR Corporation
• Inventors: Nelson, Robert W.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): HUA, LY
• Application Number:
  US07/789,553
• Time in Patent Office: 1,117 Days
• Field of Search: 371/27, 371/22.5, 371/22.1, 371/15.1, 364/717
• US Class Current: 714/739
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

An input register for an integrated circuit, the input register including a linear feedback shift register (LFSR) connected between the IC input pads and the user logic internal to the IC. The LFSR is configured as a polynomial function generator to provide a series of pseudo random test patterns to the IC internal logic. The output of the LFSR is also provided to a compare/weights logic circuit which (1) generates a stop count signal upon the receipt of a predetermined bit pattern from the LFSR, (2) generates a plurality of weighting signals by combining selected bits from the output of the LFSR, and (3) selects the feedback signal which is provided to the LFSR to determine the characteristic polynomial and degree of the polynomial implemented by the LFSR.

Claims

1. An input register for an integrated circuit, said integrated circuit including a plurality of input pads and an internal logic block, said input register comprising:

a programmable polynomial function generator for generating successive pseudo random data patterns to be supplied to said internal logic block, said programmable polynomial function generator implementing a polynomial to determine a sequence for the successive pseudo random patterns; and

logic circuitry connected to receive the output of said programmable polynomial function generator for selecting a feedback signal to be provided back to said programmable polynomial function generator to select a characteristic polynomial and a polynomial bit length to be implemented by said programmable polynomial function generator.

2. The input register according to claim 1, further comprising:

compare logic circuitry connected to receive the output of said programmable polynomial function generator for generating a stop count signal upon the receipt of a predetermined bit pattern from said polynomial function generator.

3. A method for determining a selectable seed value for a linear feedback shift register (LFSR) configured to generate a first known succession of pseudo random data patterns, said selectable seed value producing a predetermined stop pattern at the conclusion of a predetermined number of count cycles, said method comprising the steps of:

forming a computer model of the reciprocal of said LFSR for generating a second succession of pseudo random data patterns, said second succession being the inverse of said first succession; and

counting through said second succession of pseudo random data patterns beginning with said predetermined stop pattern for said predetermined number of count cycles to arrive at said selectable seed value.

4. In an input register for an integrated circuit, said input register comprising a plurality of input cells connected together to form a pseudo random pattern generator and means connected to receive said pseudo random data for generating a stop count signal upon the receipt of a predetermined stop pattern, a method for generating a predetermined number of pseudo random data patterns, said method comprising the steps of:

determining a start value required to produce said predetermined number of pseudo random data patterns concluding with said predetermined stop pattern, said step of determining said start value including the steps of;

forming a computer model of the reciprocal of said LFSR for generating an inverse succession of pseudo random data patterns;

counting through said inverse succession of pseudo random data patterns beginning with said predetermined stop pattern for said predetermined number of pseudo random data patterns to arrive at said start value; and

preloading said LFSR with said start value.