Computer with transparent power-saving manipulation of CPU clock

• US 5,369,771 A
• Filed: 12/23/1991
• Issued: 11/29/1994
• Est. Priority Date: 12/23/1991
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Gettel, Steven K.
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Auve, Glenn A.
• Application Number:
  US07/813,380
• Time in Patent Office: 1,072 Days
• Field of Search: 395/750, 364/707, 364/273.1, 364/DIG. 1, 364/948.8, 364/DIG. 2, 371/66, 371/12, 371/14
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system having power management control features which include states of normal clock speed operation, slow clock speed operation, and stop-clock operation based on input/output activity, system bus activity, and program parameters. The system detects inactivity over a period of time and places the system in one of the states to provide for power conservation and accessibility by a user.

Claims

1. A computer system, comprising:

(a) a central processing unit (CPU);

(b) a clock electrically connected to said CPU, said clock having first and second non zero operating frequencies, where said first frequency is greater than said second frequency;

(c) a system timer electrically connected to said CPU;

(d) a system counter electrically corrected to said CPU; and

(e) a clock control in electronic communication with said CPU;

wherein said clock control performs the steps of;

(i) recognizing at least four states for the computer system, said states including;

a ready state, a global standby time out state, a low speed state, and a stop clock state;

(ii) adjusting the frequency of said clock to said first frequency while the computer system is in said ready state, to said second frequency while the computer system is in said global standby time out and low speed states, and to zero while the computer system is in said stop dock state;

(iii) switching the computer system from said ready state or said low speed state to said global standby time out state, if said system timer times out without a system event occurring;

(iv) switching the computer system from said low speed state to said ready state and resetting said timer if an IO event occurs; and

(v) switching the computer system from said global standby time out state to said stop clock state if no system event or IO event occurs, but switching to said low speed state otherwise.

2. The system of claim 1, wherein:

(a) said system timer is in hardware including a register whose contents determine a timeout interval of said system timer; and

(b) said system counter is in software and whose contents are programmable.

3. The system of claim 1, further comprising:

(a) a suspended state recognized by said clock control with said clock stopped, said clock control switching said system from said stop clock state to said suspended state if a suspend time out occurs prior to a break event but switching to said ready state if a break event occurs prior to suspend time out; and

(b) said clock control switching from said suspended state to said ready state upon the occurrence of a resume event.

4. The system of claim 3, wherein:

(a) said break events are interrupts from a keyboard, a communication port, a real time clock, or a mouse.

5. The system of claim 1, further comprising:

(a) a transient stop clock state recognized by said clock control with said clock stopped, said clock control switching said system from said ready or low speed states to said transient stop clock state when a CPU Idle call occurs, and switching from said transient stop clock state to said low speed state when an interrupt occurs.

6. The system of claim 1, wherein:

(a) said first frequency is a integral multiple of said second frequency.

7. The system of claim 6, wherein:

(a) said integral multiple equal 8.

8. The system of claim 1, wherein:

(a) said system events are interrupts from a keyboard, a communication port, a disk drive, or a mouse; and

(b) said IO events are activity in a keyboard, a communication port, a disk drive, or a mouse.

9. A computer system comprising:

a central processor unit (CPU);

a clock electrically connected to said CPU, said clock having normal, slow and stopped speeds;

system timer electrically connected to said CPU;

a system counter, in electronic communication with said CPU;

a power management controller, (power management) coupled to said timer, counter, and clock, said power management putting said clock into said slow speed and decrementing said counter when said timer times out, said power management stopping said clock when said timer times out and when said counter has counted down;

suspend timers; and

wherein said power management keeps said clock stopped when said suspend timers time out prior to a break event, and said power management puts said clock in said normal speed when a resume event occurs after said suspend timers time out.

10. A computer system comprising:

a central processor unit (CPU);

a clock electrically connected to said CPU, said clock having normal, slow and stopped speeds;

a system timer electrically connected to said CPU;

a system counter, in electronic communication with said CPU;

a power management controller, (power management) coupled to said timer, counter, and clock, said power management putting said clock into said slow speed and decrementing said counter when said timer times out, said power management stopping said clock when said timer times out and when said counter has counted down;

a CPU Idle call connection to BIOS; and

wherein said power management stops said clock when a CPU Idle call issues when said clock is in normal or slow speed, and said power management puts said clock into said slow speed when an interrupt occurs following said CPU Idle call.