Method of making thin film transistors

• US 5,371,025 A
• Filed: 09/03/1992
• Issued: 12/06/1994
• Est. Priority Date: 09/06/1991
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: Gold Star Co., Ltd. (LG Corporation)
• Inventors: Sung, Kang H.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US07/940,060
• Time in Patent Office: 824 Days
• Field of Search: 437/40, 437/41, 437/101, 437/909, 437/982, 437/187, 430/317, 430/327, 430/330, 148/DIG. 102
• US Class Current: 438/160
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of making thin film transistors, capable of reducing the extent of channel overlap between a gate electrode and source/drain regions, thereby achieving an improvement in signal-to-noise ratio. The method uses a impurity ion doping process and a process for forming a silicide layer using a refractory metal, so as to form source and drain electrodes in a self-aligned manner, with respect to the gate electrode. In order to avoid a channel overlap from occurring between the gate electrode and the source and drain electrodes, a photoresist pattern is subjected to a baking, which photoresist pattern defines an insulating layer pattern serving as a channel passivation layer to determine the of a channel region and the widths of source and drain regions. By the baking, the photoresist pattern flows outwardly so that its width is approximately equal to the length of the gate electrode.

Claims

1. A method of making a thin film transistor comprising the steps of:

forming a gate electrode on an insulating transparent substrate;

forming a first insulating layer, an amorphous silicon layer and a second insulating layer in turn on the gate electrode and the insulting transparent substrate;

coating a photoresist over the second insulating layer and performing a back substrate exposure using the gate electrode as a photo shield mask to form a photoresist pattern;

baking the photoresist pattern to flow outwardly so that it has a width approximately equal to a length of the gate electrode in order to prevent a channel overlap;

etching the second insulating layer using the baked photoresist pattern as a mask to form a second insulating layer pattern serving as a channel passivation layer;

removing thee photoresist pattern from the second insulating layer pattern;

forming an impurity-doped amorphous silicon layer in the amorphous silicon layer at opposite sides of the second insulating layer pattern;

depositing a refractory metal layer on the second insulating layer pattern and the impurity-doped amorphous silicon layer and consequently forming a silicide layer between the impurity-doped amorphous silicon layer and the refractory metal layer; and

patterning the refractory metal layer to form refractory metal layer patterns at opposite sides of the second insulating layer pattern to serve as a source electrode and a drain electrode.

2. A method of making a thin film transistor in accordance with claim 1, wherein the material of the first and second insulating layers is silicon nitride.

3. A method of making a thin film transistor in accordance with claim 1, wherein the material of the insulating transparent substrate is selected from the group consisting of glass and quartz.

4. A method of making a thin film transistor accordance with claim 1, wherein the material of the gate electrode is selected from a group consisting of platinum, chromium, molybdenum, aluminum and conductively dope silicon.

5. A method of making a thin film transistor accordance with claim 1, wherein the material of the refractory metal layer is selected from the group consisting of platinum, chromium and molybdenum.

6. A method of making a thin film transistor in accordance with claim 1, wherein the patternings of the second insulating layer and refractory metal layer is achieved by using a dry etching method.

7. A method of making a thin film transistor in accordance with claim 6, wherein the dry etching method is a reactive ion etching method.

8. A method of making a thin film transistor in accordance with claim 7, wherein the reactive ion etching method uses an etching gas containing no oxygen.

9. A method of making a thin film transistor in accordance with claim 1, further comprising the step of annealing the refractory metal layer after the deposition of the refractory metal layer, to increase the thickness of the silicide layer.

10. A method of making a thin film transistor accordance with claim 1, wherein the patterning of the refractory metal layer is achieved so that the widths of the refractory metal layer patterns serving as the source electrode and the drain electrode are less than those of the silicide layer disposed at opposite sides of the second insulating layer pattern.

11. A method of making a thin film transistor in accordance with claim 1, wherein the time of performing the back substrate exposure depends on the thickness of the amorphous silicon layer.

12. A method of making a thin film transistor comprising the steps of:

forming a gate electrode on an insulating transparent substrate;

forming a first insulating layer, a polycrystalline silicon layer and a second insulating layer in turn on the gate electrode and the insulating transparent substrate;

coating a photoresist over the second insulating layer and performing a back substrate exposure using the gate electrode as a photo shield mask to form a photoresist pattern;

baking the photoresist pattern to flow outwardly so that it has a width approximately equal to a length of the gate electrode in order to prevent a channel overlap;

etching the second insulating layer using the baked photoresist pattern as a mask to form a second insulating layer pattern serving as a channel passivation layer;

removing the photoresist pattern from the second insulating pattern;

forming an impurity-doped polycrystalline silicon layer in the polycrystalline silicon layer at opposite sides of the second insulating layer pattern;

depositing a refractory metal layer on the second insulating layer pattern and the impurity-doped polycrystalline silicon layer and consequently forming a silicide layer between the impurity-doped polycrystalline silicon layer and the refractory metal layer; and

patterning the refractory metal layer to form refractory metal layer patterns at opposite sides of the second insulating layer pattern to serve as a source electrode and a drain electrode.