Process and arrangement for the Boolean realization of adaline-type neural networks

• US 5,371,413 A
• Filed: 03/04/1993
• Issued: 12/06/1994
• Est. Priority Date: 09/11/1990
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Strobach, Peter
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US07/983,531
• Time in Patent Office: 642 Days
• Field of Search: 307/201, 307/445, 395/27
• US Class Current: 326/104
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H03M 13/21 Non-linear codes, e.g. m-bit data word to n-bit code word [mBnB] conversion with error detection or error correction

Abstract

A process is stated with which ADALINE-type neural networks whose inputs are Boolean variables can be realized using Boolean functions. In addition, a purely digital circuit arrangement for realizing ADALINE-type neural networks is stated. The digital circuit arrangement can be constructed with the aid of a digital base circuit. The digital base circuit generates the set of Boolean functions which replaces a neuron for any value of its input weighting factors. A process for training the circuit arrangement is stated. It is thus possible to realize and to train ADALINE-type neural networks entirely with the aid of purely digital circuit arrangements.

Claims

1. A digital base circuit arrangement for constructing ADALINE-type neural networks, comprising:

first data input for receiving a first input signal, second data input for receiving a second input signal, clock input for receiving a clock signal and four control inputs for respectively receiving four control signals, and a data output;

means for generating, from the first and second input signals, Boolean function signals consisting of the first input signal, the second input signal, an inverse of the first input signal, an inverse of the second input signal, first, second, third and fourth AND operations of respective pairs of the first and the second input signals, the inverted first and the inverted second input signals, the first and the inverted second input signals, and the inverted first and the second input signals, and first, second, third and fourth respective inversions of the first, second, third and fourth AND operations, said means for generating connected to said first and second data inputs;

means for selecting one of said Boolean function signals as an output signal appearing on said data output, said means for selecting connected to said clock input, said four control inputs, said data output and said means for generating, wherein said output signal is dependent on values of said four control signals at a time defined by said clock signal.

2. The digital base circuit arrangement according to claim 1, wherein said means for selecting has a register having four input ports respectively connected to said four control inputs, having a clock port connected to said clock input and having an output port, and wherein said means for selecting also has a demultiplexer connected to said output port of said register and operatively connected to receive said Boolean function signals and output said output signal.

3. A digital circuit arrangement for realizing ADALINE-type neural networks, comprising:

a binary tree formed of digital base circuits, each of said digital base circuits having first and second data inputs and a data output, the binary tree having an input stage wherein respective digital base circuits receive input signals, an output stage wherein a respective digital base circuit provides an output signal, and at least one intermediate stage wherein one data input of a respective digital base circuit is connected to the output of a base circuit in a previous stage and the other data input of the respective digital base circuit is connected to the output of a further base circuit in the previous stage;

each of said digital base circuits having,

first data input for receiving a first input signal, second data input for receiving a second input signal, clock input for receiving a clock signal and four control inputs for respectively receiving four control signals, and a data output;

means for operating, from the first and second input signals, Boolean function signals consisting of the first input signal, the second input signal, an inverse of the first input signal, an inverse of the second input signal, first, second, third and fourth AND operations of respective pairs of the first and the second input signals, the inverted first and the inverted second input signals, the first and the inverted second input signals, and the inverted first and the second input signals, and first, second, third and fourth respective inversions of the first, second, third and fourth AND operations, said means for generating connected to said first and second data inputs;

means for selecting one of said Boolean function signals as an output signal appearing on said data output, said means for selecting connected to said clock input, and four control inputs, said data output and said means for generating, wherein said output signal is dependent on values of said four control signals at a time defined by said clock signal.