Differential amplifier having rail-to-rail input capability and square-root current control

• US 5,371,474 A
• Filed: 02/17/1994
• Issued: 12/06/1994
• Est. Priority Date: 05/08/1992
• Status: Expired due to Fees

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Hogervorst, Ron, Wassenaar, Roelof F., Wiegerink, Remco J., Huijsing, Johan H., Tero, John P.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/197,656
• Time in Patent Office: 292 Days
• Field of Search: 330/252, 330/253, 330/258, 330/261
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/4569 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier

Abstract

A differential amplifier contains a pair of differential portions (10 and 12) that together provide representative signal amplification across the full amplifier power-supply voltage range. Each differential portion normally contains a pair of like-polarity differentially coupled FETs (Q1 and Q2, Q3 and Q4) that divide a tail current (I_N, I_P) into a pair of main currents (I₁ and I₂, I₃ and I₄). The two FET pairs are complementary. A square-root circuit (24) controls the tail currents in such a way that the sum of their square roots is largely constant. Consequently, the amplifier transconductance is largely constant.

Claims

1. An electronic circuit operable between first and second supply voltages which constitute a power supply range including a first end range extending to the first supply voltage, a second end range extending to the second supply voltage, and an intermediate range extending between the end ranges, the circuit comprising:

first differential means for amplifying a differential input signal by largely dividing a first tail current into a pair of first main currents whose difference is representative of the input signal when its common-mode voltage V_CM is in the intermediate and first ranges;

second differential means for amplifying the input signal by largely dividing a second tail current into a pair of second main currents whose difference is representative of the input signal when V_CM is in the intermediate and second ranges; and

square-root means comprising a pair of primary control FETs having respective gate-to-source voltage whose sum is held largely constant during normal circuit operation, for controlling the tail currents so that the sum of their square roots is largely constant during circuit operation as V_CM traverses the entire intermediate range and the end ranges.

2. A circuit as in claim 1 wherein the square root means controls the tail currents such that a variation in the sum of the square roots of the tail currents is less than 10% during circuit operation as V_CM fully traverses the intermediate range.

3. A circuit as in claim 2 wherein the square-root means includes a pair of further control FETs each having respective gate electrodes and sources which control FETs each conduct respective drain currents that are held largely constant during circuit operation, the four control FETs being coupled together in a loop by way of their gate electrodes and sources, whereby the sum of their gate-to-source voltages around the loop equals zero.

4. A circuit as in claim 1 wherein the square-root means maintains the sum of the square roots of the tail currents at a largely constant value during circuit operation as V_CM traverses substantially all of the power-supply range.

5. A circuit as in claim 1 wherein the first differential means progressively goes from a substantially non-amplifying state to a substantially full-amplification state, while the second differential means does the opposite, as V_CM moves fully through the intermediate range towards the first supply voltage, and vice versa as V_CM moves fully through the intermediate towards the second supply voltage.

6. A circuit as in claim 4 wherein the first differential means provides substantially no amplification when V_CM is in the second end range, and the second differential means provides substantially no amplification when V_CM is in the first end range.

7. A circuit as in claim 1 further including summing means for combining the main currents to produce at least one output current.

8. A circuit as in claim 1 wherein:

the first differential means comprises a pair of like-polarity differentially coupled first main field-effect transistors (FETs) that differentially respond to the input signal by largely dividing the first tail current between the first main currents; and

the second differential means comprises a pair of like-polarity differentially coupled second main FETs that differentially respond to the input signal by largely dividing the second tail current between the second main currents, the second main FETs being complementary to the first main FETs.

9. A circuit as claimed in claim 8 wherein the primary control FETs each conduct respective drain currents and wherein the square-root means sets the tail currents at values respectively largely proportional in magnitude to the drain currents of the primary control FETs.

10. A circuit as in claim 9 wherein the tail currents are respectively largely equal in magnitude to the drain currents of the primary control FETs.

11. A circuit as claimed in claim 1 wherein the square-root means includes a pain of further like-polarity control FETs, each having respective gate electrodes and sources, and wherein the four control FETs are coupled together in a loop by way of their gate electrodes and sources, whereby the sum of their gate-to-source voltages around the loop equals zero.

12. A circuit as in claim 11 wherein the gate electrodes of two of the control FETs are coupled together, the sources of these two control FETs being respectively coupled to the gate electrodes of the other two control FETs whose sources are coupled together.

13. A circuit as in claim 12 wherein the control FETs each conduct respective drain currents and wherein the square-root means sets the tail currents respectively largely equal in magnitude to the drain currents of two of the control FETs, the drain currents of the other two control FETs being held largely constant during circuit operation.

14. A circuit as in claim 11 wherein the gate electrodes of two of the control FETs are coupled together, the sources of the two control FETs being respectively coupled to the sources of the other two control FETs whose gate electrodes are coupled together.

15. A circuit as in claim 14 wherein the control FETs each conduct respective drain currents and wherein the square-root means sets the tail currents respectively largely equal in magnitude to the drain currents of two of the control FETs, the drain currents of the other two control FETs being held largely constant during circuit operation.

16. A circuit as in claim 1 wherein:

the first differential means comprises a pair of like-polarity first main field-effect transistors (FETs) having respective gate electrodes differentially responsive to the input signal, respective sources coupled together through a first node for jointly conducting the first tail current, and respective drains for respectively conducting the first main currents; and

the second differential means comprises a pair of like-polarity second main FETs having respective gate electrodes differentially responsive to the input signal, respective sources coupled together through a second node for jointly conducting the second tail current, and respective drains for respectively conducting the second main currents, the second main FETs being complementary to the first main FETs.

17. A circuit as in claim 16 wherein the square-root means comprises:

steering means for adjusting a current path to the first node in response to changes in V_CM ; and

control means for providing the current path with a current determinative of the first tail current and for providing the second tail current at the second node.

18. A circuit as in claim 17 wherein the control means comprises said pair of primary control FETs having like polarity, the control means setting the tail currents at respective values largely equal in magnitude to the drain currents of the primary control FETs.

19. A circuit as in claim 18 wherein the control means includes a pair of further control FETs each having respective gate electrodes and sources which control FETs each conduct respective drain currents that are held largely constant during circuit operation, the four control FETs being coupled together in a loop by way of their gate electrodes and sources, whereby the sum of their gate-to-source voltages around the loop equals zero.

20. A circuit as in claim 19 wherein the steering means comprises:

a steering transistor having a first flow electrode coupled to the first node, a second flow electrode coupled to the control means, and a control electrode for regulating current transmission between the flow electrodes in response to a reference voltage so as to set up the current path; and

a current source coupled between the first node and the second supply voltage.

21. A circuit as in claim 20 wherein the steering transistor is a bipolar transistor.

22. A circuit as in claim 16 wherein the square-root means comprises:

sensing means for producing an adjustment signal representative of changes in V_CM ; and

control means responsive to the adjustment signal for respectively providing the first and second nodes with the first anti second tail currents at values dependent on V_CM.

23. A circuit as in claim 22 wherein the control means comprises said pair of primary control FETs having like-polarity, the control means setting the tail currents at respective values largely equal in magnitude to the drain currents of the primary control FETs.

24. A circuit as in claim 23 wherein the control means includes a pair of further control FETs each having respective gate electrodes and sources which control FETs each conduct respective drain currents that are held largely constant during circuit operation, the four control FETs being coupled together in a loop by way of their gate electrodes and sources, whereby the sum of their gate-to-source voltages around the loop equals zero.

25. A circuit as in claim 24 wherein the sensing means comprises a differential amplifier for producing the adjustment signal as a differential signal in response to the difference between a reference voltage and the voltage at one of the nodes.

26. A circuit as in claim 1 wherein said gate-to-source voltages are largely independent of the input signal.

27. A circuit as claimed in claim 26, wherein said square root means includes only a single pair of said primary control FETs.

28. An electronic circuit operable between first and second supply voltages which constitute a power supply range including a first end range extending to the first supply voltage, a second end range extending to the second supply voltage, and an intermediate range extending between the end ranges, the circuit comprising:

first differential means for amplifying a differential input signal by largely dividing a first tail current into a pair of first main currents whose difference is representative of the input signal when its common-mode voltage V_CM is in the intermediate and first ranges;

second differential means for amplifying the input signal by largely dividing a second tail current into a pair of second main currents whose difference is representative of the input signal when V_CM is in the intermediate and second ranges; and

square root means comprising four like-polarity control FETs, each having respective gate electrodes and sources, coupled together in a loop by way of their gate electrodes and sources, whereby the sum of their gate-to-source voltages around the loop equal zero, for controlling the tail currents so that the sum of their square roots is largely constant during circuit operation as V_CM traverses the entire intermediate range and the end ranges.

29. A circuit as in claim 28 wherein the gate electrodes of two of the control FETs are coupled together, the sources of these two control FETs being respectively coupled to the gate electrodes of the other two control FETs whose sources are coupled together.

30. A circuit as in claim 29 wherein the control. FETs each conduct respective drain currents and wherein the square-root means sets the tail currents respectively largely equal in magnitude to the drain currents of two of the control FETs, the drain currents of the other two control FETs being held largely constant during circuit operation.

31. A circuit as in claim 28 wherein the gate electrodes of two of the control FETs are coupled together, the sources of the two control FETs being respectively coupled to the sources of the other two control FETs whose gate electrodes are coupled together.

32. A circuit as in claim 31 wherein the control FETs each conduct respective drain currents and wherein the square-root means sets the tail currents respectively largely equal in magnitude to the drain currents of two of the control FETs, the drain currents of the other two control FETs being held largely constant during circuit operation.