Digital-signal-processing camera

• US 5,371,540 A
• Filed: 10/08/1993
• Issued: 12/06/1994
• Est. Priority Date: 04/19/1990
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Co. (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Co. (Panasonic Holdings Corporation)
• Inventors: Tamura, Akihiro, Kitamura, Yoshinori, Morimura, Atsushi
• Primary Examiner(s): Harvey, David E.
• Application Number:
  US08/133,786
• Time in Patent Office: 424 Days
• Field of Search: 358/160, 358/21 R, 358/213.11, 358/213.13, 358/213.15, 358/213.17, 358/213.18, 358/163, 348/222, 348/518, 348/914
• US Class Current: 348/222.1
• CPC Class Codes: H04N 5/0675 for mixing the synchronising signals with the picture signal or mutually electrical gates H03K17/00
• CPC Class Codes: H04N 5/77 between a recording apparatus and a television camera
• CPC Class Codes: H04N 5/91 Television signal processing therefor
• CPC Class Codes: Y10S 348/914 Delay for equalization

Abstract

In the present invention, a drive circuit 12 drives a solid-state image-pickup element 11 in synchronism with a synchronizing signal generated by a synchronizing signal generation circuit 13, and the solid-state image-pickup element 11 issues an output signal prior to an end time of a horizontal blanking period by a time period T_A. This output signal is processed in a digital signal processing circuit 14 and is issued as a picture signal. At that time, the picture signal is delayed from the synchronizing signal by a time period (T_B -T_A) owing to the signal processing, whereas the synchronizing signal is delayed by a delay circuit 15, in which a delay time made by subtracting a time period T_A from a delay time T_B of the digital signal processing circuit 14 is given, and can be issued in a proper timing for a picture signal output of the digital signal processing circuit 14. Further, by incorporating the delay circuit 15 in an LSI which constitutes the digital signal processing circuit 14, a circuit-construction can be minimized and a disturbance, which is given to the picture signal by the synchronizing signal, can be remarkably eliminated.

Claims

1. A digital-signal-processing camera comprising:

a synchronization circuit for generating a synchronizing signal;

a solid-state image-pickup element;

a drive circuit for driving said solid-state image-pickup element to initiate generation of an output signal at a point in time in a time period T_A, said time period T_A being a time period within a horizontal blanking period T_X and occurring prior to an end time of said horizontal blanking period, said time period T_A and horizontal blanking period T_X having the relationship 0<

T_A <

T_X ;

signal processing means for processing said output signal generated from said solid state image-pick up element and generating a corresponding picture signal having a delay time period T_B such that T_B >

T_X ; and

a delay circuit for delaying said synchronizing signal by a time period T_C, equal to T_B -T_A, said delay circuit and said processing means being provided in a single chip so that disturbances in said picture signal caused by said synchronizing signal are reduced.

2. A digital-signal-processing camera in accordance with claim 1, wherein said signal processing means includes a digital-signal-processing circuit and an analog-signal-processing circuit.

3. A digital-signal-processing camera in accordance with claim 1, wherein said delay circuit and said processing means circuitry are separated on said chip such that said picture signal remains undisturbed by the presence of said synchronizing signal.