Time delayed digital video system using concurrent recording and playback
First Claim
1. In combination,means for generating a substantially continuous sequence of a digital television input signal values,a source of control commands,a television signal utilization device, anda variable delay circular storage buffer having an input port connected to receive said digital television input signal values and an output port connected to supply a delayed replica of said input signal values to said utilization device following a variable delay interval, the duration of said interval being selectable in response to said control commands, said circular storage buffer comprising, in combination:
- an addressable digital memory,a programmed processor,memory access means for continuously writing said sequence of digital television input signal values into said addressable digital memory, at a sequence of writing addresses established by said processor and for concurrently reproducing and supplying to said output port an output sequence of previously written ones of signal values read from said addressable digital memory at a sequence of different reading addresses established by said processor, andmeans for supplying said output sequence to said output port,wherein said programmed processor includes means responsive to said control commands for varying the relative locations of said reading and writing addresses to selectively alter said variable delay interval.
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0 Petitions
Accused Products
Abstract
A broadcast recording and playback device employing a "circular buffer" which constantly records one or more incoming audio or video program signals and a microprocessor for accessing the memory to read a playback signal from the circular buffer to display programming material delayed from its receipt by a selectable delay interval. The circular buffer is implemented by a digital memory. Subsystem comprising the combination of a semiconductor RAM memory and a disk memory operated under the control of a microprocessor such that incoming signals are constantly recorded as received while, at the same time, delayed signals are being read from the memory subsystem at a different memory location selected by a microprocessor to provide a user-selected time delay. A plurality of input signal processors provides one or more programming signals to the memory subsystem in compressed digital form and a separate output signal processor converts the compressed digital information read from the memory into a form suitable for display. The audio/video buffer system operates under the control of a microprocessor which accepts commands from a remote command device or a connected host computer.
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Citations
8 Claims
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1. In combination,
means for generating a substantially continuous sequence of a digital television input signal values, a source of control commands, a television signal utilization device, and a variable delay circular storage buffer having an input port connected to receive said digital television input signal values and an output port connected to supply a delayed replica of said input signal values to said utilization device following a variable delay interval, the duration of said interval being selectable in response to said control commands, said circular storage buffer comprising, in combination: -
an addressable digital memory, a programmed processor, memory access means for continuously writing said sequence of digital television input signal values into said addressable digital memory, at a sequence of writing addresses established by said processor and for concurrently reproducing and supplying to said output port an output sequence of previously written ones of signal values read from said addressable digital memory at a sequence of different reading addresses established by said processor, and means for supplying said output sequence to said output port, wherein said programmed processor includes means responsive to said control commands for varying the relative locations of said reading and writing addresses to selectively alter said variable delay interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification