Three dimensional high performance interconnection package
First Claim
1. A three dimensional electronic package structure comprising:
- a plurality of assemblies;
each of said plurality of assemblies comprises a substrate having a first and second opposing surface and a plurality of electronic devices disposed on at least one of said first and said second surfaces;
each of said plurality of assemblies is disposed adjacent another of said plurality of assemblies so that one of said first and said second opposing surfaces of one of said adjacent assemblies is adjacent one of said first and said second opposing surfaces of the other of said adjacent assemblies;
an electrical interconnection means is disposed between said adjacent assemblies;
said electrical interconnection means comprises a dielectric material having first and second opposing surfaces and a plurality of electrical conductors extending from said first to said second opposing surface of said electrical interconnection means;
said electrical interconnection means provides electrical interconnection between said adjacent assemblies.
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Accused Products
Abstract
The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection electrically interconnecting each assembly. The electrical interconnection formed from an elastomeric interposer having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection is disposed over the array of electronic devices so that the electrical interconnection between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection between adjacent assemblies. Methods for fabricating the electrical interconnection as a stand alone elastomeric sheet are described.
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Citations
25 Claims
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1. A three dimensional electronic package structure comprising:
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a plurality of assemblies; each of said plurality of assemblies comprises a substrate having a first and second opposing surface and a plurality of electronic devices disposed on at least one of said first and said second surfaces; each of said plurality of assemblies is disposed adjacent another of said plurality of assemblies so that one of said first and said second opposing surfaces of one of said adjacent assemblies is adjacent one of said first and said second opposing surfaces of the other of said adjacent assemblies; an electrical interconnection means is disposed between said adjacent assemblies; said electrical interconnection means comprises a dielectric material having first and second opposing surfaces and a plurality of electrical conductors extending from said first to said second opposing surface of said electrical interconnection means; said electrical interconnection means provides electrical interconnection between said adjacent assemblies. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. The structure comprising:
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a first and second assembly; an electrical interconnection means; said first assembly is disposed adjacent said second assembly so that a first surface of said first assembly is adjacent a second surface of said second assembly; each of said first and second assemblies comprises; a substrate having first and second opposing faces; a substrate contains electrical conductors; said first surface and said second surface have a plurality of electrical contact locations disposed thereon; a plurality of electronic devices disposed on said first surface; said electrical interconnection means comprises; a layer of elastomeric material having first and second opposing surfaces; said layer has a plurality of apertures extending from said first surface to said second surface of said layer; a plurality of electrical contact locations on a first side and a second side of said layer electrically interconnected by a plurality of conductors extending from said first surface to said second surface of said layer; said electrical interconnection means is disposed on said first side of said first substrate so that said electronic devices on said first surface of said first substrate are disposed in said apertures in said electrical interconnection means; said electrical contact locations on said second side of said layer of said electrical interconnection means are electrically interconnected with electrical contact locations on said first side of said substrate of said first assembly; said electrical contact locations on said first side of said layer of said electrical interconnection means are electrically interconnected with electrical contact locations on said second side of said substrate of said second assembly. - View Dependent Claims (18, 19, 20, 21)
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22. A structure comprising:
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a substrate having a plurality of contact locations thereon; an electrical interconnection means; said electrical interconnection means comprises a dielectric material having first and second opposing surfaces and a plurality of electrical conductors extending from said first to said second opposing surfaces of said electrical interconnection means; each of said plurality of electrical conductors has a first end at said first surface; each of said first ends of said plurality of conductors has a protuberance with a flattened surface; said flattened surface is in electrical contact with at least one of said plurality of contact locations. - View Dependent Claims (23, 24, 25)
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Specification