Computer with power saving function

• US 5,371,693 A
• Filed: 10/13/1992
• Issued: 12/06/1994
• Est. Priority Date: 10/11/1991
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakazoe, Masayo
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US07/959,903
• Time in Patent Office: 784 Days
• Field of Search: 364/707
• US Class Current: 713/321
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

If there is neither a key input from a keyboard nor a command input from a CPU within a predetermined period of time, a keyboard controller generates an NMI request for sleep control. The CPU executes the NMI request in accordance with an NMI routine stored in a ROM. If the CPU is in an idle state, a sleep mode is set.

Claims

1. A computer which executes a sleep mode for reducing power consumption of a central processing unit (CPU), comprising:

data input means for inputting a key code;

a keyboard controller including determining means for determining whether the key code is input from the data input means at a predetermined time interval, and output means for outputting a request signal to the CPU when the determining means determines an absence of signals including the determination that no key code is input from the data input means within the predetermined time interval;

a register storing status data discriminating whether the CPU is in an idle state;

reading means for reading the status in response to the request signal output from the keyboard controller; and

execution means for executing the sleep mode when the status read by the reading means indicates the CPU is in the idle state.

2. A computer according to claim 1, further comprising means for executing a HALT instruction when the execution means executes the sleep mode.

3. A computer according to claim 2, further comprising means for changing a clock signal supplied to the CPU from a first clock signal to a second clock signal, said second clock signal being slower than the first clock signal, in response to the HALT instruction from the means for executing a HALT instruction.

4. A computer according to claim 1, wherein the data input means includes a keyboard.

5. A computer according to claim 1, wherein the determining means further further comprises means for detecting whether a command is input to the keyboard controller from the CPU at the predetermined time interval, and the output means outputs the request signal when the determining means determines that no key code from the data input means and no command from the CPU is input within the predetermined time interval.

6. A computer which executes a sleep mode for reducing power consumption of a central processing unit (CPU), comprising:

data input means for inputting a key code;

a keyboard controller including counting means for counting a time period during which no key code is input from the data input means, the counting means being reset when the key code is input from the data input means or a count value is counted up to predetermined value, the keyboard controller outputting a request signal to the CPU when the count value is counted up to the predetermined value;

a register storing status data discriminating whether the CPU is in an idle state;

reading means for reading the status in response to the request signal output from the keyboard controller; and

execution means for executing the sleep mode when the status read by the reading means indicates the CPU is in the idle state.

7. A computer according to claim 6, further comprising means for executing a HALT instruction when the execution means executes the sleep mode.

8. A computer according to claim 7, further comprising means for changing a clock signal supplied to the CPU from a first clock signal to a second clock signal, said second clock signal being slower than the first clock signal, in response to the HALT instruction from the means for executing a HALT instruction.

9. A computer according to claim 6, wherein the data input means includes a keyboard.

10. A computer according to claim 6, further comprising means for resetting the counting means when a command is input to the keyboard controller from the CPU.

11. A computer which executes a sleep mode for reducing power consumption of a central processing unit (CPU), comprising:

data input means for inputting a key code;

a keyboard controller determining an absence of signals including a determination that no key code is input from the data input means at a predetermined time interval, and outputting a request signal to the CPU when the absence of signals is determined by the keyboard controller within the predetermined time interval;

a register storing status data discriminating whether the CPU is in an idle state; and

a memory storing an interrupt routine program, the CPU and the interrupt routine program together providing a reading means for reading the status in response to the request signal output from the keyboard controller, and execution means for executing the sleep mode when the status read by the reading means indicates the CPU is in the idle state.

12. A computer according to claim 11, wherein the CPU and the interrupt routine program comprise a means for executing a HALT instruction when the execution means executes the sleep mode.

13. A computer according to claim 12, further comprising means for changing a clock signal supplied to the CPU from a first clock signal to a second clock signal, said second clock signal being slower than the first clock signal, in response to the HALT instruction from the means for executing a HALT instruction.

14. A computer according to claim 11, wherein the data input means includes a keyboard.

15. A computer according to claim 11, wherein the keyboard controller further comprises means for determining whether a command is input to the keyboard controller from the CPU at the predetermined time interval, and for outputting the request signal when no key code from the data input means and no command from the CPU is input within the predetermined time interval.