Internal voltage generator for a non-volatile semiconductor memory device

• US 5,371,705 A
• Filed: 05/24/1993
• Issued: 12/06/1994
• Est. Priority Date: 05/25/1992
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kobayashi, Shinichi, Nakayama, Takeshi, Futatsuya, Tomoshi, Miyawaki, Yoshikazu, Terada, Yasushi
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/066,300
• Time in Patent Office: 561 Days
• Field of Search: 365/189.11, 365/189.07, 365/230.06, 365/189.09, 365/226, 365/185
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

Claims

1. A semiconductor device, comprising:

an output circuit operating with voltage signals on a first and a second supply line as operating power supply voltages for producing a signal of a level of a voltage on one of the first and second supply lines in accordance with an input signal;

means for transmitting a signal of either of a first voltage level and a second voltage level onto the first supply line; and

shifting means in response to a voltage shifting toward the first voltage level on the first supply line for shifting in voltage level a third voltage level signal on the second supply line toward the first voltage level.

2. A semiconductor device according to claim 1, wherein said shifting means includes

first means provided between a node for supplying a voltage of the second voltage level and the first supply line for generating a voltage signal as a function of the voltage level on the first supply line at a first node,

second means provided between a node for supplying a voltage of the third level and the first node for transferring a voltage signal on the first node to a second node, and

amplifying means operating with voltage signals of the second and third voltage signals as operating power supply voltages, for amplifying the signal on the second node onto the second supply line.

3. A semiconductor device according to claim 2, wherein said first means includes

a resistance element between the node for supplying the voltage of the second voltage level and the first node, and

conduction means provided between the first node and the first supply line, and responsive to the voltage on the first supply line for conducting to change a voltage level at the first node according to the voltage level on the first supply line when the voltage level on the first supply line attains a predetermined level.

4. A semiconductor device according to claim 3, wherein said conduction means includes a resistance-connected field effect transistor.

5. A semiconductor device according to claim 3, wherein said conduction means includes a diode-connected field effect transistor connected between the first node and the first supply line in a forward direction.

6. A semiconductor device according to claim 3, wherein said conduction means includes a field effect transistor having a conduction terminal and a control terminal coupled together to the first supply node and another conduction terminal coupled to the first node, and a substrate region connected to receive a voltage of the second voltage level.

7. A semiconductor device according to claim 2, wherein said second means includes

a first field effect transistor of a first conductivity type having a conduction terminal coupled to receive a voltage of the third voltage level, another conduction terminal connected to the second node, and a control gate coupled to receive a voltage of the second voltage level, and

a second field effect transistor of a second conductivity type having a conduction terminal coupled to said first node, another conduction terminal coupled to the second node, and a control gate connected to receive a voltage of the second voltage level.

8. A semiconductor device according to claim 1, wherein said output circuit includes

latch circuit means for latching the input signal and for generating an output signal of a voltage level of either of the first and second voltage levels in accordance with the latched input signal.

9. A semiconductor device according to claim 8, wherein said output circuit further includes means for holding an input node of the latch circuit means in an electrically floating state after latching of the input signal by the latch circuit means.

10. A semiconductor device according to claim 8, wherein said output circuit further includes means for holding an input node of the latch circuit means at a voltage level of the second voltage level in an electrically floating state.

11. A semiconductor device according to claim 1, wherein said shifting means includes:

a precharging means for precharging a first node at a voltage of the third voltage level,

coupling means for capacitively coupling the first node with the first supply line, and

holding means for holding a voltage level of the second supply line at the same level as the voltage level at the first node.

12. A semiconductor device according to claim 11, wherein said holding means includes:

comparing means for comparing the voltage signals on the first node and the second supply line and for amplifying the voltage difference between the first node and the second supply line, and

establishing means responsive to an output of the comparing means for establishing a voltage level on the second supply line such that the voltage difference becomes naught.

13. A semiconductor device according to claim 11, wherein said holding means includes:

a first field effect transistor of a first conductivity type having a control gate connected to the first node,

a second field effect transistor of a second conductivity type having a conduction terminal connected to another conduction terminal of the first field effect transistor, and another conduction terminal connected to receive a voltage at the third voltage level,

a third field effect transistor of the first conductivity type having a conduction terminal connected to another conduction terminal of the first field effect transistor and to receive a voltage of the second voltage level, and a control gate connected to the second supply line,

a fourth field effect transistor of the second conductivity type having a control gate and a conduction terminal connected together to a control gate of the second field effect transistor, and another conduction terminal connected to receive a voltage at the third voltage level, and

an inverter having an input connected to the another conduction terminal of the first field effect transistor and an output connected to the second supply line.

14. A semiconductor device according to claim 1, wherein said output circuit includes a latch circuit means for latching the input signal.

15. A semiconductor device according to claim 14, wherein said latch circuit means includes;

a first field effect transistor of a first conductivity type having one conduction terminal connected to said second supply line, another conduction terminal connected to a first node receiving the input node, and a control terminal connected to a second node,

a second field effect transistor of a second conductivity type having one conduction terminal connected to said first node, another conduction terminal connected to the first supply line, and a control gate connected to said second node,

a third field effect transistor of the first conductivity type having one conduction terminal connected to said second supply line, another conduction terminal connected to the second node, and a control gate connected to said first node, and

a fourth field effect transistor of the second conductivity type having one conduction terminal connected to the first supply line, another conduction terminal connected to said second node, and a control gate connected to said first node, said second node serving as a node for generating an output signal of the output circuit.

16. A semiconductor device according to claim 1, wherein said shifting means includes means responsive to the second voltage level signal on the first supply line for transmitting the third voltage level signal on the second supply line and responsive to transition from the second voltage level signal to the first voltage level signal on the first supply line for changing the third voltage level signal to the second voltage level signal.

17. A semiconductor device according to claim 1, wherein the first voltage level is a negative voltage level, the second voltage level is a ground voltage level, and the third voltage level is a positive power supply voltage level.

18. A semiconductor device according to claim 1, wherein the second voltage level is a positive power supply voltage level, the first voltage level is a voltage level higher than the second voltage level, and the third voltage level is a ground voltage level.

19. A non-volatile semiconductor memory device, comprising:

a plurality of non-volatile memory cells arranged in a matrix of rows and columns,

a plurality of word lines arranged on respective rows, each of the word lines connecting memory cells on an associated row,

row decoder means for decoding an address signal,

drive means provided for each said word line and responsive to an output of the row decoder means for transferring a voltage signal on either of a first supply line and a second supply line onto a selected word line,

generator means responsive to an predetermined operation mode instructing signal for generating and supplying a voltage signal of a first level onto the first supply line, and

adjusting means in response to the generation of the first level voltage signal for adjusting a voltage on the second supply line so as to reduce a voltage difference between the first and second supply lines.

20. A non-volatile semiconductor memory device according to claim 19, wherein said drive means includes

voltage switch means using the voltages on the first and second supply lines as operating power supply voltages and responsive to the output of the decoder means for producing a signal of a level of the voltage on one of the first and second supply lines, and

transfer means responsive to a signal produced by the voltage switch means for transferring a voltage signal on the first supply line to the associated word line.

21. A non-volatile semiconductor memory device according to claim 19, wherein said adjusting means includes,

first means provided between a node for supplying a voltage of the second voltage level and the first supply line for generating a voltage signal as a function of the voltage level on the first supply line at a first node,

second means provided between a node for supplying a voltage of a third level and the first node for transferring a voltage signal on the first node to a second node, and

amplifying means operating with voltage signals of the second and third voltage signals as operating power supply voltages, for amplifying the signal on the second node onto the second supply line.

22. A non-volatile semiconductor memory device according to claim 21, wherein said first means includes

a resistance element connected between the node for supplying the voltage of the second voltage level and the first node, and

conduction means provided between the first node and the first supply line, and responsive to the voltage on the first supply line for conducting to change a voltage level at the first node according to the voltage level on the first supply line when the voltage level on the first supply line attains a predetermined level.

23. A non-volatile semiconductor memory device according to claim 22, wherein said conduction means includes a resistance-connected field effect transistor.

24. A non-volatile semiconductor memory device according to claim 22, wherein said conduction means includes a diode-connected field effect transistor connected between the first node and the first supply line in a forward direction.

25. A non-volatile semiconductor memory device according to claim 22, wherein said conduction means includes a field effect transistor having a conduction terminal and a control terminal coupled together to the first supply line and another conduction terminal coupled to the first node, and a substrate region connected to receive a voltage of the second voltage level.

26. A non-volatile semiconductor memory device according to claim 21, wherein said second means includes

a first field effect transistor of a first conductivity type having a conduction terminal coupled to receive a voltage of the third voltage level, another conduction terminal connected to the second node, and a control gate coupled to receive a voltage of the second voltage level, and

a second field effect transistor of a second conductivity type having a conduction terminal coupled to said first node, another conduction terminal coupled to the second node, and a control gate connected to receive a voltage of the second voltage level.

27. A non-volatile semiconductor memory device according to claim 20, wherein said voltage switch means includes

latch circuit means for lathing the input signal and generating an output signal of a voltage level of either of the first and second voltage levels in accordance with the latched input signal.

28. A non-volatile semiconductor memory device according to claim 27, wherein said voltage switch means further includes means for holding an input node of the latch circuit means in an electrically floating state after latching of the input signal by the latch circuit means.

29. A non-volatile semiconductor memory device according to claim 27, wherein said voltage switch means further includes means for holding an input node of the latch circuit means at a voltage-level of the second voltage level in an electrically floating state.

30. A non-volatile semiconductor memory device according to claim 19, wherein said adjusting means includes:

a precharging means for precharging a first node at a voltage of a third voltage level,

coupling means for capacitively coupling the first node with the first supply line, and

holding means for holding a voltage level of the second supply line at the same level as the voltage level at the first node.

31. A non-volatile semiconductor memory device according to claim 30, wherein said holding means includes:

coupling means for comparing the voltage signals on the first node and the second supply line and for amplifying the voltage difference between the first node and the second supply line, and

establishing means responsive to an output of the comparing means for establishing a voltage level on the second supply line such that the voltage difference becomes naught.

32. A non-volatile semiconductor memory device according to claim 30, wherein said holding means includes:

a first field effect transistor of a first conductivity type having a control gate connected to the first node,

a second field effect transistor of a second conductivity type having a conduction terminal connected to another conduction terminal of the first field effect transistor, and another conduction terminal connected to receive a voltage at the third voltage level,

a third field effect transistor of the first conductivity type having a conduction terminal connected to another conduction terminal of the first field effect transistor and to receive a voltage of the second voltage level, a control gate connected to the second supply line,

a fourth field effect transistor of the second conductivity type having a control gate and a conduction terminal connected together to a control gate of the second field effect transistor, and another conduction terminal connected to receive a voltage at the third voltage level, and

an inverter having an input connected to the another conduction terminal of the first field effect transistor and an output connected to the second supply line.

33. A non-volatile semiconductor memory device according to claim 19, wherein the first voltage level is a negative voltage level, and said adjusting means changes a power supply voltage to a ground potential level voltage.

34. A non-volatile semiconductor memory device according to claim 19, wherein the first voltage level is a voltage level higher than a positive power supply voltage, and said adjusting means changes a ground potential level voltage to the positive power supply voltage.

35. A non-volatile semiconductor memory device according to claim 20, wherein said voltage switch means includes:

shifting means for shifting in voltage level an output of said decoder means toward the first voltage level on the first supply line, and

amplifying means using the voltages on the first and second supply lines as operating power supply voltages and amplifying a voltage signal received from the shifting means through bi-level processing.

36. A non-volatile semiconductor memory device according to claim 34, wherein said shifting means includes a first voltage divider including resistance elements connected in series between the first supply line and a node receiving a voltage at a third level, and a second voltage divider including resistance elements connected in series between the first supply line and a node receiving a voltage of the second level.

37. A semiconductor device comprising:

an output circuit responsive to an input signal for generating an output signal of a voltage level of either of voltages on a first supply line and a second supply line;

a first voltage supply means for supplying a first voltage of either one of a first level and a second level on the first supply line; and

a second voltage supply means for detecting a level of a voltage supplied from said first voltage supply means and for supplying a second voltage of either one of the second level and a third level on the second supply line according to the result of detection.

38. A semiconductor device according to claim 37, wherein said second supply means includes means for supplying the second voltage of the second level when detecting that the first supply means supplies the first voltage of the first level.

39. A semiconductor device according to claim 37, wherein said first level is a negative voltage level, said second level is a ground voltage level, and said third level is a positive power supply voltage level.

40. A semiconductor device according to claim 38, wherein said second level is a positive power supply voltage level, said third voltage is a ground voltage level, and said first level is a predetermined voltage level higher than said positive power supply voltage.

41. A non-volatile semiconductor memory device, comprising:

a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns;

a plurality of word lines provided corresponding to said rows, each of said word lines connecting memory cells of a corresponding row;

predecode means operating with a first level voltage and a second level voltage as operating power supply voltages for predecoding an address signal to generate a first predecode signal and a second predecode signal;

voltage generating means responsive to an operation mode instructing signal for generating a third level voltage;

level convert means for converting the first and second predecode signals into a first shift signal and a second shift signal of the first and third voltage levels while maintaining the logical value of the first and second predecode signals;

decode means operating with the first and third level voltages as operating supply voltages for decoding the first predecode signal to generate a row selection signal; and

drive means responsive to said row selection signal for transferring the second shift signal onto a word line selected by said row selection signal.

42. A non-volatile semiconductor memory device according to claim 41, wherein said level convert means includes means responsive to generation of the third level voltage for shifting a level of the second level voltage to a level of the first level voltage and instead shifting a level of the first level voltage to a level of the third level voltage.

43. A non-volatile semiconductor memory device according to claim 41, wherein the third level voltage is a negative level voltage, the first level voltage is a ground level voltage, and the second level voltage is a positive power supply voltage.

44. A non-volatile semiconductor memory device according to claim 41, wherein said level convert means includes means responsive to generation of the third level voltage for shifting a level of the second level voltage to a level of the third level voltage.

45. A non-volatile semiconductor memory device according to claim 44, wherein said second level voltage is a positive power supply voltage, said first level voltage is a ground level voltage, and said third level voltage is a voltage higher than said positive power supply voltage.

46. A non-volatile semiconductor memory device according to claim 41, wherein said voltage generating means includes first means responsive to a first instructing signal for generating a negative level voltage, and second means responsive to a second instructing signal for generating a positive high voltage higher than a positive power supply voltage, and wherein said level convert means includes;

control means responsive to generation of said negative level voltage for converting the second level voltage into the first level voltage and responsive to generation of said positive high voltage for converting the second voltage into the positive high voltage; and

latch means operating with an output voltage of said control means and an output voltage of said first means as operating power supply voltages for latching and level-shifting a received predecode signal.

47. A non-volatile semiconductor memory device according to claim 46, wherein said level convert means further includes means responsive to one of the second instructing signal and generation of the negative level voltage for isolating said latching means from the decode means.

48. A non-volatile semiconductor memory device according to claim 41, wherein said level convert means includes means responsive to the operation mode instructing signal for reversing a logic level of the second predecode signal.

50. A method according to claim 48, wherein said step of shifting includes the steps of detecting transmission of the first voltage level signal on the first supply line;

and

changing the third voltage level signal to the second voltage level signal.

49. A method of operating a semiconductor device including

an output circuit operating with voltage signals on a first and a second supply line as operating power supply voltages for producing a signal of a level of a voltage on one of the first and second supply lines in accordance with an input signal, comprising the steps of:

transmitting a signal of either of a first voltage level and a second voltage level onto the first supply line; and

shifting in response to a voltage shifting toward the first voltage level on the first supply line for shifting in voltage level a third voltage level signal on the second supply line toward the first voltage level.

51. A method of operating a semiconductor device, comprising the steps of:

responsive to an input signal for generating an output signal of a voltage level of either of voltages on a first supply line and a second supply line;

supplying a first voltage of either one of a first level and a second level on the first supply line; and

detecting a level of a voltage supplied from said first voltage supply means and for supplying a second voltage of either one of the second level and a third level on the second supply line according to the result of detection.