Universal protocol programmable communications interface

• US 5,371,736 A
• Filed: 12/21/1992
• Issued: 12/06/1994
• Est. Priority Date: 12/21/1992
• Status: Expired due to Fees

• Current Assignee: ABB Incorporated (ABB Limited)
• Original Assignee: ABB Power T&D Limited (ABB Limited)
• Inventors: Evan, Shabtai
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US07/993,702
• Time in Patent Office: 715 Days
• Field of Search: 370/79, 370/83, 370/84, 370/85.1, 370/82, 340/825.06
• US Class Current: 370/470
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A general purpose programmable communications interface designed to support a wide variety of serial synchronous and asynchronous communication protocols. A universal protocol communications (UPC) interface is designed to operate on a VME bus in conjunction with a CPU board which contains the application software that utilizes the communications capabilities of the UPC interface. Per channel DMA is available on input/output lines of the interface together with bit level control for message processing so that a variety of bit oriented communications protocols may be supported by simple reconfiguration of the receiver/transmitter of the programmable UPC interface. In a preferred embodiment, a dynamically variable bit length shift register is used to organize the received and transmitted data into serial packets of the appropriate size on a per channel basis independent of the actual width of the shift register. Reconfiguration for different protocols is accomplished by simply changing a bit count value stored in a bit counter which counts the number of serial data bits received or transmitted in each data word by the dynamically variable bit length shift registers of the transmit and receive circuitry.

Claims

1. A universal protocol communications interface controlled by a host processor so as to provide serial synchronous and asynchronous data communication over a plurality of data communications channels between data communications devices having the same or different bit oriented data communications protocol as said host processor, comprising:

a host interface for selectively providing read and write access to said host processor; and

a data communications controller comprising;

a data buffer connected to said host processor via said host interface;

a memory for storing data for passage to/from said data communications devices;

a DMA device for providing addresses to data stored in said memory;

a data bus for providing data communication among said buffer, said memory and said DMA device;

a controller for arbitrating among different requests for access to said data bus; and

at least one programmable synchronous/asynchronous receiver/transmitter connected to said data bus so as to provide data communications between said data bus and a plurality of data communications devices over said plurality of data communications channels, each programmable synchronous/asynchronous receiver/transmitter having a programmable bit protocol length for data packets transmitted or received thereby, said bit protocol length being programmed independently for each of said plurality of data communications channels so as to provide serial data communications over each data communications channel in data packets having the bit protocol length of the data communications device connected thereto.

2. A circuit as in claim 1, comprising a plurality of said data communications controllers, wherein each data communications controller comprises one of said programmable synchronous/asynchronous receiver/transmitters for each of said data communications channels.

3. A circuit as in claim 2, wherein each programmable synchronous/asynchronous receiver/transmitter comprises a receiving dynamically variable bit length shift register for shifting onto said data bus from a data communications channel serial input data in data packets having a known bit protocol length and a transmitting dynamically variable bit length shift register for shifting from said data bus into said data communications channel serial output data in data packets having said known bit protocol length.

4. A circuit as in claim 3, wherein each programmable synchronous/asynchronous receiver/transmitter further comprises a receive bit counter which stores said known bit protocol length and counts bits of said serial input data inputted into said receiving dynamically variable bit length shift register and a transmit bit counter which stores said known bit protocol length and counts bits of said serial output data output from said transmitting dynamically variable bit length shift register.

5. A circuit as in claim 4, wherein each programmable synchronous/asynchronous receiver/transmitter further comprises a receive controller for controlling said receiving dynamically variable bit length shift register to shift onto said data bus said serial input data in data packets having said known bit protocol length for storage in said memory, and a transmit controller for controlling said transmitting dynamically variable bit length shift register to shift into said data communications channel said serial output data in data packets having said known bit protocol length.

6. A circuit as in claim 5, wherein said receiving dynamically variable bit length shift register has a physical bit length which does not equal said known bit protocol length and accordingly shifts least significant bits of said serial input data to the least significant bits of said receiving dynamically variable bit length shift register prior to shifting said serial input data onto said data bus.

7. A circuit as in claim 1, wherein said host processor comprises a VME computer backplane connected to said host interface via a VME bus.

8. A circuit as in claim 7, wherein said host interface comprises a controller for controlling the direction of data flow between said VME bus and said data bus through said host interface and for providing system interrupts to said host interface and said data communications controller in response to interrupt requests from said host processor.

9. A circuit as in claim 1, wherein said programmable bit protocol length is variable to accommodate data packets having from 1 to 256 bits.

10. A method of transmitting serial synchronous and asynchronous data from a host computer over a plurality of data communications channels to one or more data communications devices having the same or different bit oriented data communications protocol as said host computer, comprising the steps of:

for each data communications channel, loading a bit protocol length of the data communications device to which that channel is connected;

setting a desired data rate;

starting at a user defined address, loading a memory of said host computer with data to be transmitted as output data to said data communications device;

loading a DMA device with said user defined address and the number of words of data which are to be read from said memory starting at said user defined address;

enabling data transmission;

transferring words of data having a word bit length of said memory to a dynamically variable bit length shift register starting at said user defined address;

shifting data from said dynamically variable bit length shift register into said data communications channel until a number of bits equal to said bit protocol length has been transferred; and

once said number of bits equal to said bit protocol length have been shifted into said communications channel, reloading said dynamically variable bit length shift register with further words of data from said memory.

11. A method of receiving serial synchronous and asynchronous data by a host computer via a plurality of data communications channels, each data communications channel being connected to a data communications device having the same or different bit oriented data communications protocol as said host computer, comprising the steps of:

for each data communications channel, loading a bit protocol length of the data communications device to which that channel is connected;

setting a desired data rate;

determining an address of a memory of said host computer to which input data from said data communications device is to be stored;

loading a DMA device with said memory address and the number of words of input data from said data communications device which are to be written into said memory starting at said memory address;

enabling data receipt;

transferring words of input data having a word bit length of said data communications device to a dynamically variable bit length shift register;

shifting data from said dynamically variable bit length shift register into said memory until a number of bits equal to said bit protocol length has been stored in said memory; and

once said dynamically variable bit length shift register has shifted said number of bits equal to said bit protocol length to said memory, loading said dynamically variable bit length shift register with further words of data having said word bit length from said data communications device.

12. A universal protocol communications interface controlled by a host processor so as to provide serial synchronous and asynchronous data communication over a plurality of data communications channels between data communications devices having the same or different bit oriented data communications protocol as said host processor, comprising:

a host interface for selectively providing read and write access to said host processor; and

a data communications controller comprising;

a data buffer connected to said host processor via said host interface;

a memory for storing data for passage to/from said data communications devices;

a DMA device for providing addresses to data stored in said memory;

a data bus for providing data communication among said buffer, said memory and said DMA device;

a controller for arbitrating among different requests for access to said data bus; and

at least one programmable synchronous/asynchronous receiver/transmitter connected to said data bus so as to provide data communications between said data bus and a plurality of data communications devices over said plurality of data communications channels, each programmable synchronous/asynchronous receiver/transmitter having a programmable bit protocol length which is variable from 1 to 256 bits and programmed independently for each of said plurality of data communications channels so as to provide serial data communications over each data communications channel in the bit protocol length of the data communications device connected thereto.