Packet mode digital data receiver

• US 5,371,763 A
• Filed: 11/13/1992
• Issued: 12/06/1994
• Est. Priority Date: 11/13/1992
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Ota, Yusuke, Swartz, Robert G.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): MAY, TIMOTHY
• Application Number:
  US07/976,037
• Time in Patent Office: 753 Days
• Field of Search: 375/76, 375/98, 307/268, 307/357, 307/358, 307/359, 455/239.1, 455/240.1, 328/149, 330/11
• US Class Current: 375/319
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier
• CPC Class Codes: H04B 10/695 Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection

Abstract

A dc-coupled packet mode digital data receiver, for use with an optical bus, uses a peak detector(s) to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A reset circuit resets the peak detector(s) and other circuits of the receiver in response to an end-of-packet reset signal, thereby enabling the reception of closely-spaced burst date packets which have greatly differing power levels.

Claims

1. A digital data receiver comprising

a dc-coupled differential input amplifier circuit having first input means for receiving a digital packet data input signal, second input means for receiving a reference signal, and output means for outputting a data output signal;

a detector means for detecting and storing a peak amplitude of said data output signal and for generating said reference signal; and

reset means, responsive to an end-of-packet reset signal, for discharging said peak amplitude of said data output signal stored by said detector means to a non-zero dc voltage substantially equal to a dc bias voltage which corresponds to a voltage stored by said detector means during an absence of a received data input signal.

2. The receiver of claim 1 wherein said reset means includes

course reset means for discharging said stored data output signal at a high discharge rate until it is within a predetermined voltage difference of said dc bias voltage;

and

fine reset means for discharging said stored data output signal at a low discharge rate, until said dc bias voltage is reached.

3. The receiver of claim 1 wherein said first detector means includes

capacitor means for storing the peak amplitude of said data output signal and wherein

said reset means includes

switchable current source means for discharging said capacitor means in response to said reset signal and switchable so that it is off at all other times.

4. The receiver of claim 3 wherein said reset means has a first power consumption during said reset signal and has a second power consumption, which is less than said first power consumption, during the absence of said reset signal.

5. The receiver of claim 3 wherein said switchable current source means has a capacity to substantially discharge said capacitor within no more than four bit time periods of said data input signal.

6. The receiver of claim 3 wherein said switchable current source means includes

a comparator amplifier having a first input connected to said reference signal and a second input connected to a second reference signal equal to said dc bias voltage, an output of said comparator amplifier controlling said switchable current source means to discharge said capacitor means when said reference signal exceeds said second reference signal.

7. The receiver of claim 6 wherein said comparator means is arranged to discharge said capacitor means to said dc bias voltage which is less than one percent of the difference between the peak amplitude of said data output signal and said reference signal.

8. The receiver of claim 6 wherein

said reference signal is generated using a pair of reference amplifier circuits, a first reference amplifier circuit being implemented identical to and operating under identical operating conditions as said differential amplifier circuit and a second reference amplifier circuit being implemented identical to and operating under identical operating conditions as said first detector means, said first and second reference amplifier circuitry being interconnected in the same manner as said differential amplifier circuit and said first detector means.

9. The receiver of claim 1 further including

output amplifier means having an input connected to said input amplifier circuit output means and an output for providing a receiver output signal and

means for disabling said output amplifier means in response to said reset signal.

10. The receiver of claim 1 implemented as part of an integrated circuit.

11. The receiver of claim 1 wherein said data input signal is a current signal and wherein said input amplifier circuit is a transimpedance amplifier circuit.

12. The receiver of claim 1 wherein said data input signal is a voltage signal and wherein said input amplifier circuit is a voltage amplifier circuit.

13. A digital data receiver comprising

a dc-coupled differential input amplifier circuit having first input means for receiving a digital packet data input signal, second input means for receiving a first reference signal, and output means for outputting a data output signal;

detector means for detecting and storing a peak amplitude of said data output signal and for generating said first reference signal;

first reset means, responsive to an end-of-packet reset signal, for discharging said data output signal stored by said detector means to a dc bias voltage which is within a predetermined voltage difference of a second reference voltage; and

second reset means, responsive to said end-of-packet reset signal, for discharging said peak amplitude of said data output signal stored by said detector means to said second reference voltage wherein said second reference voltage corresponds to a voltage stored by said detector means during an absence of a received data input signal.

14. A digital data receiver comprising

a dc-coupled differential amplifier circuit having first input means for receiving a digital data input signal, second input means for receiving a reference signal, and output means for outputting a data output signal;

first detector means for detecting and storing a peak amplitude of said data output signal and for generating said first reference signal; and

second detector means for detecting and storing a second peak amplitude of said data output signal and for generating a second reference signal;

means, responsive to said first and second reference signals, for shunting a portion of a dc or low frequency current of said data input signal from said first input means; and

reset means, responsive to an end-of-packet reset signal, for discharging said first and second peak amplitudes stored, respectively, by said first and second detector means to a non-zero dc voltage substantially equal to a dc bias voltage which corresponds to a voltage stored by said first and second detector means during an absence of a received data input signal.

15. The receiver of claim 14 wherein said reset means includes

coarse reset means for discharging said stored data output signal on each detector means at a first discharge rate until it is within a predetermined voltage difference of said dc bias voltage;

and

fine reset means for discharging said stored data output signal at a second discharge rate, smaller than said first rate, until said dc bias voltage is reached.

16. The receiver of claim 14 wherein said first and second detector means each includes

capacitor means for storing the peak amplitude of said data output signal and wherein

said reset means includes

separate switchable current source means for each detector means for discharging the capacitor means in response to said reset signal and switchable so that it is off when said reset signal is not present.

17. The receiver of claim 16 wherein said reset means has a first power consumption during said reset signal and has a second power consumption, which is less than said first power consumption, during the absence of said reset signal.

18. The receiver of claim 16 wherein each switchable current source means has a capacity to substantially discharge its capacitor within no more than four bit time periods of said data input signal.

19. The receiver of claim 16 wherein each switchable current source means includes

a comparator amplifier having a first input connected to said first reference signal and a second input connected to a third reference signal, equal to said dc bias voltage, an output of said comparator amplifier controlling said switchable current source means to discharge said capacitor means when said first reference signal exceeds said third reference signal.

20. The receiver of claim 19 wherein said comparator means is arranged to discharge the capacitor means to said dc bias voltage which is within a one percent of the difference between the peak amplitude of said data output signal and said third reference signal.

21. The receiver of claim 19 wherein

said third reference signal is generated using a pair of reference amplifier circuits, a first reference amplifier circuit being implemented substantially identical to and operating under substantially identical operating conditions as said differential amplifier circuit and a second reference amplifier circuit being implemented substantially identical to and operating under substantially identical operating conditions as said first detector means, said first and second reference amplifier circuitry being interconnected in the same manner as said differential amplifier circuit and said first detector means.

22. The receiver of claim 14 further including

output amplifier means having an input connected to the output means of said input amplifier circuit and an output for providing a receiver output signal and

means for disabling said output amplifier means in response to a reset signal from said reset means.

23. The receiver of claim 14 wherein

said output means of said input amplifier circuit includes a first and second differential output means;

said first detector means connects to said first output means; and

said second detector connects to said second output means.

24. The receiver of claim 23 wherein said first and second detector means are each implemented using identical circuit apparatus and operating under identical operating conditions and which are implemented as part of an integrated circuit.

25. The receiver of claim 14 wherein said digital data input signal is a current signal and wherein said input amplifier circuit is a transimpedance amplifier circuit.

26. The receiver of claim 14 wherein said digital data input signal is a voltage signal and wherein said input amplifier circuit is a voltage amplifier circuit.

27. An optical signal receiver comprising

means for receiving a digital optical signal,

means for converting the received digital optical signal into an electronic data signal,

a dc-coupled differential input amplifier circuit having first input means for receiving said electronic data signal, second input means for receiving a first reference signal, and output means for outputting a data output signal;

first detector means for detecting and storing a first peak amplitude of said data output signal and for generating said first reference signal;

second detector means for detecting and storing a second peak amplitude of said data output signal and in response thereto shunting a portion of a current from said data input signal, said current having a frequency which is less than a predetermined frequency; and

reset means, responsive to an end-of-packet reset signal, for discharging said first and second peak amplitudes stored, respectively, by said first and second detector means to a non-zero dc voltage substantially equal to a dc bias voltage which corresponds to a voltage stored by said detector means during an absence of a received data input signal.

28. An optical signal receiver comprising

means for receiving a digital optical signal,

means for converting the received digital optical signal into an electronic data signal,

a dc-coupled differential input amplifier circuit having first input means for receiving said electronic data signal, second input means for receiving a reference signal, and output means for outputting a data output signal;

detector means for detecting and storing a peak amplitude of said data output signal and for generating said reference signal; and

reset means, responsive to an end-of-packet reset signal, for discharging said data output signal stored by said detector means to a non-zero dc voltage substantially equal to a dc bias voltage which corresponds to a voltage stored by said detector means during an absence of a received data input signal.

29. A digital data receiver comprising

a dc-coupled differential amplifier circuit having first input means for receiving a digital data input signal, second input means for receiving a first reference signal, and output means for outputting a data output signal;

first detector means for detecting and storing a peak amplitude of said data output signal and for generating said first reference signal;

second detector means for detecting and storing a second peak amplitude of said data output signal and for generating a second reference signal;

means, responsive to said first and second reference signals, for shunting a portion of a current of said data input signal from said first input means, said current having a frequency which is less than a predetermined frequency;

first reset means, responsive to an end-of-packet reset signal, for discharging said data output signal stored by said first detector means to a dc voltage which is within a predetermined voltage difference of a third reference voltage; and

second reset means, responsive to said end-of-packet reset signal, for discharging said data output signal stored by said second detector means to said third reference voltage wherein said third reference voltage corresponds to a voltage stored by said detector means during an absence of a received data input signal.