Data storage device and method of accessing the data storage device

• US 5,371,793 A
• Filed: 07/07/1993
• Issued: 12/06/1994
• Est. Priority Date: 07/10/1992
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kimura, Masatoshi
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US08/086,891
• Time in Patent Office: 517 Days
• Field of Search: 380/3, 380/4, 380/23, 380/24, 380/25, 380/49, 380/50, 235/379, 235/380, 235/382, 340/825.31, 340/825.34, 365/189.07, 365/195, 365/201
• US Class Current: 713/193
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/3576 Multiple memory zones on card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G07F 7/1025 Identification of user by a PIN code

Abstract

A semiconductor data storage device has a common memory for storing processed data, an attribute memory for storing attribute data, a buffer circuit connected to a bus of the common memory and a bus of the attribute memory, and a control circuit connected to the bus of the common memory and the bus of the attribute memory for accessing each of the common memory and the attribute memory. The control circuit controls connection and isolation of the buffer circuit. According to a method of accessing the semiconductor data storage device, when a secret code is input from the terminal unit through the buffer circuit, the control circuit isolates the buffer circuit, thereafter compares the secret code with an identification code stored in the attribute memory, and sets the buffer circuit in the connected state to allow the terminal unit to access the common memory if the secret code and the identification code coincide with each other and maintains the buffer circuit in the isolated state to inhibit the terminal unit from accessing the common memory if the secret code and the identification code do not coincide with each other.

Claims

1. A method of controlling access to a data storage device comprising:

storing an identification code in first region of an attribute memory incorporated in the data storage device;

disconnecting a common memory of the data storage device from a terminal unit when a secret code is input to the data storage device from the terminal unit;

storing the secret code in a second region of the attribute memory, separate from the first region of the attribute memory;

comparing the second code and the identification code to each other; and

connecting the common memory to the terminal unit to allow access to the common memory if the secret code and the identification code coincide with each other and maintaining the bus of the common memory and the terminal unit disconnected, inhibiting the terminal unit from accessing the common memory, if the secret code and the identification code do not coincide with each other.

2. The method of controlling access to a data storage device according to claim 1 wherein a most significant bit address signal indicates division of the attribute memory into the first region and the second region including prohibiting access by the terminal unit to the first region of the attribute memory.

3. A data storage device comprising:

a common memory for storing processed data;

an attribute memory having a first memory region in which an identification code is stored and a second memory region, separate from the first memory region, in which attribute data including common memory capacity and common memory access speed are stored;

buffer means connected to said common memory and said attribute memory for controlling input of data to and output of data from said common memory and said attribute memory;

control means connected to and controlling said common memory, said attribute memory, and said buffer means, said control means controlling said buffer means and said attribute memory, upon receipt of a secret code by said data storage device from a terminal unit, to store the second code in the second memory region of said attribute memory, to isolate and thereby prevent said buffer means from receiving additional data, to read the identification code and the secret code from said attribute memory, to compare the identification code and the secret code read from the attribute memory, to generate coincidence information indicating whether the identification code and the secret code coincide, and, if the identification code and the secret code do not coincide, continuing to isolate said buffer means, thereby denying access to said common memory by the terminal unit, and if the identification code and the secret code do coincide, connecting said buffer means to provide access to said common memory by the terminal unit for writing data into and reading data from said common memory.

4. The data storage device according to claim 3 wherein said control means receives a most significant bit address signal from said attribute memory indicating division between the first and second regions of said attribute memory for prohibiting access to the first region of said attribute memory by the terminal unit.

5. The data storage device according to claim 3 wherein said common memory comprises a volatile memory and said attribute memory comprises a non-volatile memory.

6. The data storage device according to claim 3 wherein said buffer means includes an input buffer circuit connected to an address bus of said common memory and an address bus of said attribute memory, and an input/output buffer circuit connected to a data bus of said common memory and a data bus of said attribute memory.

7. The data storage device according to claim 3 comprising:

a battery for supplying electrical power to said common memory; and

a power supply control circuit for supplying electrical power from a terminal unit to said common memory and for supplying electrical power from said battery to said common memory when the power supply from the terminal is shut off.

8. The data storage device according to claim 3 wherein said control means controls said buffer means and said attribute memory to store the secret code in the second memory region of said attribute memory.

9. The data storage device according to claim 8 wherein said control means stores the coincidence information in the second memory region of said attribute memory.

10. The data storage device of claim 8 wherein said control means controls said buffer means to prohibit access by the terminal unit to the first memory region of said attribute memory.