×

Polygon tiling engine

  • US 5,371,840 A
  • Filed: 04/21/1994
  • Issued: 12/06/1994
  • Est. Priority Date: 04/26/1990
  • Status: Expired due to Term
First Claim
Patent Images

1. In a computer graphics display system, wherein the system includes a high speed processor which provides a plurality of vertex points and a symbol code, an improved apparatus for tiling polygons comprising:

  • a. logic means coupled to receive the symbol code, said logic means generating a symbol type signal in response to the symbol code;

    b. start/stop detection means operably connected to the high speed processor for receiving said plurality of vertex points and providing start and stop signals in response to said plurality of vertex points which mark starting and ending addresses for a polygon being tilted;

    c. means for storing user defined objects coupled to receive the symbol type signal at a first input, said storing means having a user defined object address output which is activated if the symbol type signal is representative of a user defined object;

    d. means for generating polygon addresses comprising a first input coupled to receive the symbol type signal, a second input coupled to receive the start and stop signals, and a third input coupled to said user defined object address output, said polygon address generating means generating polygon addresses in response to the first, second and third inputs and outputting the polygon addresses through a polygon address output;

    e. storage means for constructing a list of points for user defined objects, said storage means having an input connected to said polygon address output of said polygon address generating means, said storage means providing an end-of-polygon bit at the end of each face of a user defined polygon as constructed in the list of points at a linked list output, said storage means further providing user defined polygon addresses at said linked list output;

    f. multiplexing means coupled at a first input to the polygon address output of said polygon address generating means, and at a second input to said linked list output, said multiplexing means further comprising a multiplexed object address output, said multiplexing means controlled in response to said symbol type signal so as to switch through said linked list output if a user defined object is being tiled, until said end-of-polygon bit is encountered otherwise switching through said polygon address output; and

    g. buffered memory means having a first input coupled to receive the plurality of vertex points from the high speed processor, and coupled at a second input to said multiplexed object address output, said buffered memory means comprising an output which provides a selected sequence of vertex points selected from the plurality of vertex points, the sequence of vertex points being determined by the multiplexed object address output.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×