Program execution control system

• US 5,371,862 A
• Filed: 02/26/1992
• Issued: 12/06/1994
• Est. Priority Date: 02/27/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suzuki, Shinichiro, Takeuchi, Yoichiro
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): Toplu, Lucien
• Application Number:
  US07/841,511
• Time in Patent Office: 1,014 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/375
• US Class Current: 712/234
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification

Abstract

A program execution control system is provided for a processing unit of a computer. An exclusive register has a plurality of 1-bit flag in which true and false data can be individually set and which can individually specify a flag for determining whether execution of each instruction in the program is canceled or not for each instruction. This provides for an integer, logic operation and comparison and a memory for storing an instruction word which contains a flag specifying filed in the exclusive register for determining whether execution of the instruction is canceled or not based on a value stored in the exclusive register, a condition is also provided specifying sub-operation code filed for an operand by use of a numeric value and a flat bit for storing a resulting value of true or false for given condition when the instruction sets the flat for setting the resultant value of truth or falsehood of the condition specified to the instruction of the condition specifying sub-operation code filed in the exclusive flat register specified to the instruction of the flag bit specifying operand field and for canceling the instruction according to at least one of a value of the exclusive register means specified to the instruction of the flat bit specifying filed indicating to cancel the instruction whether the value is "1" or "0".

Claims

1. A program execution control system for controlling the execution of and cancellation of instructions for a processing unit of a computer having a main memory and registers, comprising:

exclusive register means including a plurality of flag means in which true and false data can be individually set and which can individually be specified as a flag for determining whether execution of each instruction in the program is canceled or not for each instruction, and having a function as an operand executing at least one of an integer operation, logic operation and comparison operation;

memory means for storing an instruction word, said instruction word including a flag specifying field for specifying at least predetermined said flag means in said exclusive register means for determining whether execution of the instruction is to be canceled or not based on said exclusive register means, and further including a condition specifying sub-operation code field for specifying a predetermined condition for an operand and a flag bit specifying operand field for specifying said particular flag means in said exclusive register means storing a result of true or false for given condition when the instruction sets said flag means;

setting means for setting the result of truth or falsehood of condition specified to the instruction of said condition specifying sub-operation code field into the flag means in said exclusive flag register means specified to the instruction of said flag bit specifying operand field when an instruction determining said flag means is executed; and

canceling means coupled to said memory means for canceling the instruction according to at least one of a content of the, flag means in said exclusive register means and responsive thereto specified to the instruction of said flag bit specifying field and the content stored in said flag specifying field indicating to cancel the instruction either said flag means is "1" or "0".

2. A control system according to claim 1, wherein said flag means in said exclusive register means are constituted by flip-flops.

3. A control system according to claim 1, wherein said setting means includes:

a binary decoder having an input terminal and a plurality of output terminals, for outputting a logic value from one of said output terminals according to a value in said flag bit specifying field;

an operand comparator for outputting a preset signal based on the result of an operand value specified by said instruction word; and

a first data selector for outputting a preset output to said exclusive register means according to a relationship between said operand comparator and said operand.

4. A control system according to claim 1, wherein said canceling means includes:

a second data selector for selecting a corresponding one of said flag means according to an input value from said flag specifying field and outputting an input value from said selected flag means; and

an Ex-OR gate for outputting a canceling signal according to the input value from said flag specifying field and an input from said second data selector.

5. A control system according to claim 1, wherein said canceling means further comprises:

a memory port with inhibition input for transferring data between the main memory and a specified one of the registers in the computer, and inhibiting transferring data therebetween according to a first predetermined cancel signal; and

a write-back mechanism with inhibition input for writing back the result of an operation instruction into a particular register, and inhibiting writing-back according to a second predetermined cancel signal.

6. A control system according to claim 5, wherein said canceling means includes means for supplying a canceling signal to said write-back mechanism with inhibition input.

7. A control system according to claim 5, wherein said canceling means includes means for supplying a canceling signal to said memory port with inhibition input.

8. A control system according to claim 1, wherein said canceling means further comprises:

two program counters for fetching an instruction next to a present instruction in the program and outputting an address of said next instruction; and

a second data selector for selecting an output from one of said program counters and outputting an address of an instruction to be next fetched.

9. A control system according to claim 8, wherein said canceling means includes means for setting a branch destination address into one of said program counters which is not used now when a branch instruction is issued.

10. A control system according to claim 9, wherein said canceling means includes means for inhibiting change-over from the program counter which is now used to said program counter into which the branch destination address is set.