Look-ahead priority arbitration system and method

• US 5,371,893 A
• Filed: 12/27/1991
• Issued: 12/06/1994
• Est. Priority Date: 12/27/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rodiger, William K., Price, Donald W., Reiley, Forrest A.
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/816,358
• Time in Patent Office: 1,075 Days
• Field of Search: 395/725, 395/325, 395/425, 364/242.6, 364/DIG. 1, 364/937.01, 364/DIG. 2
• US Class Current: 710/241
• CPC Class Codes: G06F 13/368 with decentralised access control

Abstract

An improved arbitration system is disclosed for arbitrating signals at a plurality of input nodes to output nodes where each input node can access any output node. The system includes a FIFO (first-in-first-out) input queue for each node and means for arbitrating the top of each queue for providing the arbitrated output to a given node and means when the top of the input queue has no request for a given node arbitrating the requests from the next to the top entry of the input queues and providing the data from the next to top entry associated with the arbitrated request to the given node.

Claims

1. An arbitration system for selecting a single request for transmission to one output node from multiple such requests for transfer made by contending input nodes, said arbitration system comprising:

a plurality of input queues one associated with each of said contending input nodes, each such input queue for storing, in a plurality of stages, requests from its associated input node, at least two of said stages in each queue being separately accessible output stages, one stage being a head of queue stage and another stage being a next to head of queue stage;

arbitration means connected to both output stages of each queue for selecting, during a single selection cycle, a request from either a head of queue stage or a next to head of queue stage of one of said queues in accordance with a selection algorithm, said arbitration means including primary selection means for selecting a request from a head of queue stage if such a request is present in any said head of queue stage and secondary selection means for selecting a request from a next to head of queue stage in a queue selected by said algorithm in the absence, during said selection cycle, of any such request in any head of queue stage of said queues.

2. The arbitration system of claim 1 wherein:

said arbitration means includes;

first and second arbitrating circuits operating in parallel, one arbitrating circuit coupled to the head of the queue stages of said queues for selecting between contending requests in the head of the queue stages and another arbitrating circuit coupled to the next to head of queue stages for selecting between contending requests in the next to head of queue stages; and

sense means for providing a first signal at an output in response to the presence of a request in any head of queue stage of said queues and a second signal at an output in the absence of such a presence.

3. The arbitration system of claim 2 wherein:

said primary selection means includes a first set of AND gates transmitting the selection of said one arbitrating circuit to said one output node in response to said first signal; and

said secondary selection means includes a second set of AND gates providing the selection of said another arbitrating circuit to said one output node on occurrence of said second signal.

4. The arbitration system of claim 3 wherein:

said first and second arbitrating circuits each have a plurality of outputs, one output associated with each of said queues;

said set of AND gates of both the primary and secondary selection means each containing one AND gate for each of said queues with one input of each such AND gate coupled to the output associated with said queue of the appropriate one of said first and second arbitrating circuits and another input of each such AND gate connected to an output of said sense means.

5. The arbitration system of claim 4 wherein said queues are FIFO queues.

6. The arbitration system of claim 5 wherein said selection algorithm is a round robin selection algorithm.

7. A method for transferring, one at a time, to a single output node, sets of signals, made up of a request signal and data signals, said sets of signals being supplied by a plurality of requesting nodes contending for such transfer said method comprising the steps of:

a) placing said sets from each requesting node in stages of separate queues in the order in which said sets are to be transferred to the output node;

b) simultaneously selecting for transfer from said queues a first output from stages containing highest order requests for transfer to said one output node and a second output from stages containing next highest order requests for transfer to said one output node;

c) detecting the presence or absence of a request for transfer in any of said stages of said queues for containing the highest order requests;

d) transferring to said one output node data signals in said first output if the presence of a request for transfer to said one output node is detected by step c) and transferring to the output node data signals in said second output if the presence of a request is not detected by step c).

8. The method of claim 7 including selecting the first and second outputs in step b) is in accordance with a round robin algorithm.

9. The method of claim 8 including ordering said requests in said queues so that the first request in is the first request out (FIFO).