Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode

• US 5,372,962 A
• Filed: 02/01/1993
• Issued: 12/13/1994
• Est. Priority Date: 01/31/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hirota, Toshiyuki, Watanabe, Hirohito, Zenke, Masanobu, Honma, Ichirou
• Primary Examiner(s): BRENEMAN, ROBERT B
• Application Number:
  US08/011,855
• Time in Patent Office: 680 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/919, 437/977, 437/173, 437/46, 148/DIG. 138
• US Class Current: 438/398
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: Y10S 148/138 Roughened surface
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.

Claims

1. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) depositing a doped polysilicon film over said substrate for a lower electrode of said capacitor;

c) perforating a surface portion of said doped polysilicon film by using an anodizing technique so that said surface portion of said doped polysilicon film becomes porous, said anodizing technique being carried out in water solution of hydrofluoric acid ranging from 5% to 40% by volume, direct current flowing between said doped polysilicon film and a platinum cathode at several milli-ampere/cm² to hundreds milli-ampere/cm² under radiation of light onto said doped polysilicon film, said light having a range of wavelengths corresponding to from visual light to ultra violet light;

d) conformally covering at least said surface portion of said doped polysilicon film with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said doped polysilicon film.

2. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a phosphorus-doped polysilicon film for a lower electrode of said capacitor;

c) perforating a surface portion of said phosphorus-doped polysilicon film having grooves along grain boundaries of said phosphorus-doped polysilicon film by using an etching in an etchant containing phosphoric acid so that said surface portion of said semiconductor block becomes porous, and comprising the sub-steps of

c-1) introducing impurity atoms in said semiconductor block so as to segregate said impurity atoms along grain boundaries and around dislocations, and

c-2) treating said semiconductor block with an etchant having an etching rate variable with concentration of said impurity atoms for selectively removing said grain boundaries and heavily doped portions around said dislocations, thereby forming micro-recesses in said predetermined surface portions of said semiconductor block;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

3. A process as set forth in claim 2, in which said semiconductor block is formed of polysilicon, and said impurity atoms and said etchant are phosphorus and vapor containing phosphoric acid.

20. The process as set forth in claim 2, in which said etchant containing phosphoric acid is heated to about 140 degrees centigrade for perforating said surface.

4. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor, having the sub-steps of

b-1) depositing a semiconductor material which can be etched by an etchant,

b-2) depositing a substance hardly etched by said etchant on the film of said semiconductor material, and

b-3) depositing said semiconductor material to a thickness on the film of said substance, the films of said semiconductor materials and the film of said substance form in combination said semiconductor block,

c) perforating a surface portion of said semiconductor block by using an etching so that said surface portion of said semiconductor block becomes porous, having the sub-steps of

c-1) introducing impurity atoms segregated along grain boundaries and around dislocations, and

c-2) selectively etching said grain boundaries and heavily doped portions around said dislocations by using said etchant having a selectivity between heavily doped portion and lightly doped portion,

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

5. A process as set forth in claim 4, in which said sub-steps b-2) and b-3) are repeated after said sub-step b-1.

6. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor;

c) perforating a surface portion of said semiconductor block by using an etching so that said surface portion of said semiconductor block becomes porous, having the sub-steps of

c-1) ion-implanting phosphorus atoms in said semiconductor block,

c-2) annealing said semiconductor block so as to segregate said phosphorus atoms along grain boundaries and around dislocations, and

c-3) treating said semiconductor block with an isotropical etchant having an etching rate variable with concentration of said phosphorus atoms for selectively removing said grain boundaries and heavily doped portions around said dislocations, thereby forming micro-recesses in said predetermined surface portions of said semiconductor block;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

7. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor, and having the sub-steps of

b-1) depositing amorphous silicon doped with phosphorus atoms, said amorphous silicon doped with said phosphorus atoms serving as said semiconductor block, and

b-2) annealing said amorphous silicon so as to allow said phosphorus atoms to segregate along boundaries between large sized silicon grain as well as around dislocations;

c) perforating a surface portion of said semiconductor block by using an etching through treatment with an isotropic etching solution containing phosphoric acid so that said surface portion of said semiconductor block becomes porous;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

8. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a doped polysilicon block for a lower electrode of said capacitor;

c) perforating a surface portion of said doped polysilicon block by using an etching in one of water solution of ammonia and vapor of ammonia, a mixture of hydrofluoric acid and nitric acid and a mixture of hydrofluoric acid and hydrogen peroxide so that said surface portion of said doped polysilicon block becomes porous;

d) conformally covering at least said surface portion of said doped polysilicon block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said doped polysilicon block.

9. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor, comprising the sub-steps of

b-1) depositing polysilicon over a major surface of said substrate so as to form a first polysilicon film having column-like grains oriented in a vertical direction with respect to said major surface,

b-2) patterning said first polysilicon film so as to form a first polysilicon sub-block,

b-3) depositing polysilicon over the entire surface so as to form a second polysilicon film, a side surface of said first polysilicon block being covered with a part of said second polysilicon film having column-like grains oriented in a substantially parallel direction to said major surface, and

b-4) uniformly etching said second polysilicon film without any mask so that a second polysilicon sub-block is left on said side surface of said first polysilicon sub-block, said first and second polysilicon sub-blocks forming in combination said semiconductor block;

c) perforating a surface portion of said semiconductor block by using a roughening technique selected so that said surface portion of said semiconductor block becomes porous, and comprising the sub-steps of

c-1) introducing impurity atoms in said semiconductor block so as to segregate along grain boundaries and around dislocations, and

c-2) exposing said semiconductor block doped with said impurity atoms to an etchant having an etching rate variable with concentration of said impurity atoms for selectively removing said grain boundaries and heavily doped portions around said dislocations, thereby forming micro-recesses in said predetermined surface portions of said semiconductor block;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

10. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor;

c) perforating a surface portion of said semiconductor block by using a dry etching so that said surface portion of said semiconductor block becomes porous, having the sub-steps of

c-1) introducing phosphorus atoms in said semiconductor block so as to segregate along grain boundaries and around dislocations, and

c-2) exposing said semiconductor block doped with said phosphorus atoms to halogen radicals having an etched rate variable with concentration of said impurity atoms for selectively removing said grain boundaries and heavily doped portions around said dislocations, thereby forming micro-recesses in said predetermined surface portions of said semiconductor block;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

11. The process as set forth in claim 10, in which said halogen radicals are produced from halogen atoms under one of photo-exiting phenomenon, a radiation of micro-waves, a radiation of high-frequency electromagnetic waves and a plasma produced with an electron gun.

12. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) depositing a doped polysilicon film on said substrate;

c) patterning and perforating said doped polysilicon film for a lower electrode of said capacitor by using a dry etching so that a surface portion of said lower electrode becomes porous, said dry etching being carried out by using halogen radicals produced in one of a parallel plate reactive etching system, a reactive ion etching system assisted by electron cyclotron resonance, a magnetron reactive ion etching system and helicon-etching system;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

13. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor;

c) perforating a surface portion of said semiconductor block by using an anodizing technique so that said surface portion of said semiconductor block becomes porous, having the sub-steps of

c-1) preparing an electrolyte containing hydrofluoric acid at 5% to 40% by volume and a cathode,

c-2) causing said semiconductor block of polysilicon to oppose to said cathode in said electrolyte, and

c-3) causing direct current to flow between said semiconductor block and said cathode for producing micro-recesses;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

14. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) depositing a silicon film over said substrate for a lower electrode of said capacitor;

c) perforating a surface portion of said silicon film by using an anodizing technique so that said surface portion of said silicon film becomes porous, said anodizing technique being carried out in water solution of hydrofluoric acid ranging from 5% to 40% by volume, and direct current flows between said silicon film and a platinum cathode at several milli-ampere/cm² to hundreds milli-ampere/cm² ;

d) expanding micro-recesses produced in said surface portion of said silicon film comprising the sub-steps of

d-1) dipping said surface portion of said silicon film in water solution containing one of hydrogen peroxide and nitric acid for growing a thin oxide film ranging between 1 nano-meter to 2 nano-meter;

d-2) exposing said thin oxide film in hydrofluoric acid for removing said thin oxide film, and

d-3) repeating said sub-steps of d-1) and d-2);

e) conformally covering at least said surface portion of said silicon film with a dielectric layer; and

f) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said silicon film.

15. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) depositing a silicon film over said substrate for a lower electrode of said capacitor;

c) perforating a surface portion of said silicon film by using an anodizing technique so that said surface portion of said silicon film becomes porous, said anodizing technique being carried out in water solution of hydrofluoric acid ranging from 5% to 40% by volume, and direct current flows between said silicon film and a platinum cathode at several milli-ampere/cm² to hundreds milli-ampere/cm² ;

d) expanding micro-recesses produced in said surface portion of said silicon film, comprising the sub-steps of

d-1) exposing said predetermined surface portion to solution containing ammonia for growing a silicon nitride film to 1.5 nano-meters to 2.0 meters,

d-2) removing said silicon nitride film in a solution containing H₃ PO₄, and

d-3) repeating said sub-steps d-1) and d-2);

e) conformally covering at least said surface portion of said silicon film with a dielectric layer; and

f) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said silicon film.

16. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) depositing a silicon film over said substrate for a lower electrode of said capacitor;

c) perforating a surface portion of said silicon film by using an anodizing technique so that said surface portion of said silicon film becomes porous, said anodizing technique being carried out in water solution of hydrofluoric acid ranging from 5% to 40% by volume, and direct current flows between said silicon film and a platinum cathode at several milli-ampere/cm² to hundreds milli-ampere/cm² ;

d) expanding micro-recesses produced in said surface portion of said silicon film comprising the sub-steps of

d-1) creating a high temperature annealing ambience from one of non-oxidizing ambience, vacuum ambience and reducing ambience, and

d-2) recrystallizing said predetermined surface portion in said high temperature annealing ambience for producing large-sized micro-recesses;

e) conformally covering at least said surface portion of said silicon film with a dielectric layer; and

f) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said silicon film.

17. A process as set forth in claim 16, in which said high temperature annealing ambience contains hydrogen.

18. A process of fabricating a semiconductor device comprising the steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor, comprising the sub-steps of

b-1) depositing an amorphous silicon film over said substrate,

b-2) patterning said amorphous silicon film into a lower electrode serving as said semiconductor block, and

b-3) annealing said lower electrode in vacuum under application of heat to said substrate for forming hemispherical grains over a surface of said lower electrode;

c) perforating a surface portion of said semiconductor block by using a roughening technique so that said surface portion of said semiconductor block becomes porous, comprising the sub-steps of

c-1) introducing impurity atoms into said lower electrode so that said impurity atoms are segregated along grain boundaries and around dislocations, and

c-2) exposing said lower electrode to an etchant

containing phosphoric acid for perforating said lower electrode;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.

19. A process of fabricating a semiconductor device comprising the sub-steps of:

a) preparing a substrate for an integrated circuit having a capacitor;

b) forming a semiconductor block for a lower electrode of said capacitor, comprising the sub-steps of

b-1) forming a doped amorphous silicon film through a chemical vapor deposition, and

b-2) patterning said doped amorphous silicon film into a lower electrode serving as said semiconductor block;

c) perforating a surface portion of said semiconductor block by dipping said semiconductor block in an etching solution containing phosphoric acid so that said surface portion of said semiconductor block becomes porous;

d) conformally covering at least said surface portion of said semiconductor block with a dielectric layer; and

e) forming an upper electrode in such a manner as to oppose through said dielectric layer to said surface portion of said semiconductor block.