Method of making semiconductor device

• US 5,372,966 A
• Filed: 03/01/1994
• Issued: 12/13/1994
• Est. Priority Date: 03/01/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kohyama, Yusuke
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/203,944
• Time in Patent Office: 287 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/83, 437/99, 437/203, 437/919, 257/301
• US Class Current: 438/243
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

In formation of a DRAM, a silicon nitride film is used as a mask to simultaneously expose a semiconductor substrate serving as an active region where an MOSFET is formed and a portion of the periphery of a trench. Therefore, even if the alignment offset of a resist pattern occurs, an interval between adjacent memory cells does not change. The interval between the adjacent memory cells is constantly the same as that when no alignment offset of the resist patter occurs. That is, only an n-type diffusion layer of the memory cell formed at a position adjacent to the trench comes close to source and drain regions of the adjacent memory cell.

Claims

1. A method of making a semiconductor memory device comprising the step of:

(a) preparing a semiconductor substrate of a first conductivity type;

(b) forming a first insulating film over said semiconductor substrate;

(c) forming a trench in said semiconductor substrate through said first insulating film;

p1 (d) forming a second insulating film over an inner wall of said trench;

(e) filling said trench with a doped polysilicon layer;

(f) depositing a third insulating film over said first insulating film;

(g) using said third insulating film as a mask, removing said first insulating film to form an opening for defining both a transistor region and a connect region of said doped polysilicon layer at the same time;

(h) forming a transistor on said transistor region;

(i) exposing said connect region using said third insulating film as said mask; and

(j) forming a conductive layer so as to electrically connect one of source and drain regions of said transistor to said connect region.

2. The method according to claim 1, wherein said first insulating layer is silicon oxide, and said third insulating layer is silicon nitride.

3. The method according to claim 1, wherein said active region is continuous to said connect region.

4. A method of making a semiconductor memory device comprising the step of:

(a) preparing a semiconductor substrate of a first conductivity type;

(b) forming a first insulating film over said semiconductor substrate;

(c) forming a trench in said semiconductor substrate through said first insulating film;

(d) forming a second insulating film over an inner wall of said trench;

(e) filling said trench with a doped polysilicon layer;

(f) depositing a third insulating film over said first insulating film;

(g) using said third insulating film as a mask, removing said first insulating film from said semiconductor substrate so as to expose a part of said doped polysilicon layer;

(h) growing a semiconductor layer on said semiconductor substrate to provide a polycrystalline semiconductor layer on the exposed portion of said doped polysilicon layer; and

(i) forming a transistor on said semiconductor layer.

5. The method according to claim 4, wherein the step (f) defines a connect region for electrically connecting one of source and drain regions of said transistor to said doped polysilicon layer.