Low-power, jitter-compensated phase locked loop and method therefor

• US 5,373,255 A
• Filed: 07/28/1993
• Issued: 12/13/1994
• Est. Priority Date: 07/28/1993
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bray, Jeffrey P., Pendleton, Matthew A., Cozart, Steven E.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/098,974
• Time in Patent Office: 503 Days
• Field of Search: 331/1 A, 331/17, 331/25, 331/27, 307/516, 307/525, 307/526, 307/528, 328/133, 328/134
• US Class Current: 331/1.00A
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Claims

1. A low-power, jitter-compensated phase locked loop, comprising:

a phase detector having a first input for receiving a reference clock signal, a second input for receiving a loop clock signal, and an output, said phase detector providing a phase detect output signal at said output in response to a phase difference between said reference clock signal and said loop clock signal;

phase error accumulation means coupled to said phase detector, for periodically sampling said phase detect output signal with a sample clock, and for accumulating over a predetermined number of periods of said sample clock an accumulated phase error, said phase error accumulation means including a counter and a register;

said counter having an input coupled to said output of said phase detector, a clock input for receiving said sample clock, a reset input for receiving a latching clock, and an output;

said register having an input coupled to said output of said counter, a latch input terminal for receiving said latching clock, and an output coupled to an input of a loop filter;

said latching clock characterized as being derived from said reference clock signal;

said loop filter having said input coupled to said output of said register for receiving said accumulated phase error, and an output for providing a filtered output;

a voltage controlled oscillator having an input coupled to said output of said loop filter, and an output for providing a clock output signal of the phase locked loop; and

a loop divider having an input for receiving said clock output signal of the phase locked loop, and an output for providing said loop clock signal.

2. The phase locked loop of claim 1 wherein said phase detector is characterized as being an up/down phase detector, and wherein said counter is characterized as being an up/down counter.

3. The phase locked loop of claim 1 wherein a frequency of said latching clock and a frequency of said reference clock signal are equal.

4. A low-power, jitter-compensated phase locked loop, comprising:

a phase detector having a first input terminal for receiving a reference clock signal, a second input terminal for receiving a loop clock signal, and an output terminal;

a phase error accumulator having an input terminal coupled to said output terminal of said phase detector, a sample clock input terminal for receiving a sample clock, a latching clock input terminal for receiving a latching clock, and an output terminal, said phase error accumulator including a counter and a register;

said counter having an input terminal coupled to said output terminal of said phase detector, a clock input terminal for receiving said sample clock, a reset input terminal for receiving said latching clock, and an output terminal;

said register having an input terminal coupled to said output terminal of said counter, a latch input terminal for receiving said latching clock, and an output terminal coupled to an input terminal of a loop filter;

said latching clock characterized as being derived from said reference clock signal;

a voltage controlled oscillator having an input terminal coupled to an output terminal of said loop filter, and an output terminal for providing a clock output signal of the phase locked loop; and

a loop divider having an input terminal coupled to said output terminal of said voltage controlled oscillator, and an output terminal coupled to said second input terminal of said phase detector.

5. The phase locked loop of claim 4 wherein a frequency of said latching clock and a frequency of said reference clock signal are equal.

6. The phase locked loop of claim 4 wherein said phase detector is characterized as being an up/down phase detector, and wherein said counter is characterized as being an up/down counter.

7. In a phase locked loop, a method for reducing power while maintaining low jitter, comprising the steps of:

detecting a phase difference between a reference clock signal and a loop clock signal to provide a phase detect signal;

sampling said phase detect signal on a predetermined transition of a sample clock;

accumulating a plurality of samples of said phase detect signal and providing an accumulated phase error synchronously with a latching clock, said latching clock characterized as being derived from said reference clock signal;

filtering said accumulated phase error in a loop filter; and

providing a clock output signal of the phase locked loop having a frequency proportional to an output of said loop filter.

8. The method of claim 7 further comprising the step of dividing said clock output signal of the phase locked loop by a predetermined number to provide said loop clock signal.

9. The method of claim 7 wherein said step of sampling said phase detect signal on said predetermined transition of said sample clock comprises the step of selectively incrementing or decrementing a counter on said predetermined transition of said sample clock in response to said phase detect signal.

10. The method of claim 9 wherein said step of filtering said accumulated phase error in said loop filter further comprises the step of filtering said accumulated phase error in a digital loop filter.

11. A low-power, jitter-compensated phase locked loop, comprising:

a phase detector having a first input terminal for receiving a reference clock signal, a second input terminal for receiving a loop clock signal, and an output terminal, said phase detector comprising a phase detector latch for determining a phase difference between said reference clock signal and said loop clock signal;

a loop filter having an input terminal coupled to said output terminal of said phase detector, and an output terminal;

a voltage controlled oscillator having an input terminal coupled to said output terminal of said loop filter, and an output terminal for providing a clock output signal of the phase locked loop; and

a loop divider having an input terminal coupled to said output terminal of said voltage controlled oscillator, and an output terminal coupled to said second input terminal of said phase detector;

said phase detector providing an up signal in response to said phase detector latch detecting a first predetermined transition of said reference clock signal leading a second predetermined transition of said loop clock signal;

said phase detector providing a down signal in response to said phase detector latch detecting said first predetermined transition of said loop clock signal leading said second predetermined transition of said reference clock signal;

said phase detector providing a predetermined one of said up signal and said down signal in response to a metastable condition of said phase detector latch.

12. The phase locked loop of claim 11 wherein said phase detector further comprises resolution means coupled to said phase detector latch, for providing said predetermined one of said up and down signals in response to said phase detector latch being in said metastable condition during a predetermined time period.

13. The phase locked loop of claim 12 wherein said predetermined time period comprises an interval during which said loop clock signal makes said second predetermined transition.

14. The phase locked loop of claim 12 wherein said resolution means further provides said predetermined one of said up signal and said down signal in response to said phase detector latch simultaneously providing both said up signal and said down signal.

15. The phase locked loop of claim 11 further comprising a phase error accumulator coupled between said output terminal of said phase detector and said input terminal of said loop filter.

16. The phase locked loop of claim 15 wherein said phase error accumulator has an input terminal coupled to said output terminal of said phase detector, a sample clock input terminal for receiving a sample clock, a latching clock input terminal for receiving a latching clock, and an output terminal coupled to said input terminal of said loop filter.

17. In a phase locked loop, a phase detector comprising:

latching means for receiving a reference clock signal and a loop clock signal, and for providing first and second output signals thereof in response to first and second transitions of said reference clock signal and said loop clock signal, respectively;

a phase detector latch having a first input terminal for receiving said first output signal of said latching means, a second input terminal for receiving said second output signal of said latching means, a first output terminal for providing a first output signal thereof, and a second output terminal for providing a second output signal thereof;

said phase detector latch providing said first output signal thereof in response to detecting said first output signal of said latching means leading said second output signal of said latching means;

said phase detector latch providing said second output signal thereof in response to detecting said second output signal of said latching means leading said first output signal of said latching means; and

resolution means coupled to said phase detector latch, for providing an up signal in response to said first output signal of said phase detector latch, for providing a down signal in response to said second output signal of said phase detector latch, and for providing a predetermined one of said up and down signals in response to said phase detector latch being in a metastable condition during a predetermined time period.

18. The phase detector of claim 17 wherein said predetermined time period comprises an interval during which said loop clock signal makes said second transition.

19. The phase detector of claim 17 wherein said resolution means further provides said predetermined one of said up signal and said down signal in response to said phase detector latch simultaneously providing both said up signal and said down signal.

20. The phase detector of claim 17 wherein said phase detector latch comprises:

a first NAND gate having a first input terminal for receiving said first output signal of said latching means, a second input terminal, and an output terminal for providing said first output signal of said phase detector latch; and

a second NAND gate having a first input terminal coupled to said output terminal of said first NAND gate, a second input terminal for receiving said second output signal of said latching means, and an output terminal for providing said second output signal of said phase detector latch.

21. In a phase locked loop, a method for detecting a phase difference between a loop clock signal and a reference clock signal in order to provide a clock output signal with low jitter, comprising the steps of:

activating a set input of a phase detector latch in response to a first predetermined transition of the reference clock signal leading a second predetermined transition of the loop clock signal;

activating a reset input of said phase detector latch in response to said second predetermined transition of the loop clock signal leading said first predetermined transition of the reference clock signal;

providing an up signal in response to a true output of said phase detector latch;

providing a down signal in response to a complement output of said phase detector latch;

detecting a metastable condition in said phase detector latch; and

activating a predetermined one of said up signal and said down signal in response to said metastable condition in said phase detector latch.

22. The method of claim 21 wherein said step of detecting comprises the step of detecting said metastable condition as a condition in which both said up signal and said down signal are inactive during a predetermined time period.