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Remote control circuit breaker system

  • US 5,373,411 A
  • Filed: 12/23/1992
  • Issued: 12/13/1994
  • Est. Priority Date: 09/30/1991
  • Status: Expired due to Term
First Claim
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1. A remote control circuit breaker system comprising a plurality of remote control circuit breakers each including a switch responsive to a control signal for controllably completing and interrupting a respective load circuit, a plurality of pole controllers each responsive to an address signal and coupled to a respective circuit breaker and supplying said control signal to said switch, each pole controller including a status circuit responsive to actuation of said switch and supplying a status signal indicative thereof, a common controller coupled to said pole controllers and supplying said address signals, said status signal is generated after generation of said address confirming actuation of said switch in response to said control signal from said pole controller responding to said address signal, said common controller generates a sequence cycle comprising an address cycle comprising a plurality of multiplexed address signals, followed by a status cycle comprising a plurality of multiplexed status signals, such that status cycles are provided between address cycles, said status cycle begins upon completion of said address cycle, and wherein upon completion of said status cycle, the next address cycle begins, said common controller comprises a timer generating a first high frequency clock signal, a counter counting said clock signals and dividing same to provide a plurality of different lower frequency clock signals, a group of said lower frequency clock signals providing address selection signals for said multiplexed address signals, a logic gating circuit logically combining said first high frequency clock signal and one of said lower frequency clock signals and providing said address cycle and said status cycle, such that said address cycle and said status cycle are both generated by said common controller, said logic gating circuit comprises a first gate enabled by said one lower frequency clock signal during a first interval and passing said first high frequency clock signal therethrough during said first interval, and a second gate enabled by said one lower frequency clock signal during a second interval and passing said first high frequency clock signal therethrough during said second interval, said first gate being disabled during said second interval to block passage of said first high frequency clock signal therethrough, said second gate being disabled during said first interval to block passage of said first high frequency clock signal therethrough, said first and second intervals sequentially following each other in alternating relation, said first interval providing said address cycle, said second interval providing said status cycle.

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