Operational amplifier using bipolar junction transistors in silicon-on-sapphire

• US 5,374,567 A
• Filed: 05/20/1993
• Issued: 12/20/1994
• Est. Priority Date: 05/20/1993
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Cartagena, Eric N.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US08/065,321
• Time in Patent Office: 579 Days
• Field of Search: 437/31, 437/21, 437/84, 437/247, 437/32, 148/DIG. 77, 148/DIG. 150
• US Class Current: 438/311
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/66265 Thin film bipolar transistors H01L29/66242 takes precedence
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: Y10S 148/077 Implantation of silicon on sapphire
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

A method for fabricating low leakage current bipolar junction transistors of silicon-on-sapphire for efficient use in operational amplifiers utilizes all implant technology, improved silicon conditioning processing, and low temperature annealing.

Claims

1. An improvement to a method for fabricating bipolar junction transistors in silicon-on-sapphire in which base and emitter regions are formed in a silicon wafer on a sapphire substrate, the improvement including:

recrystalizing said silicon wafer prior to the formation of said base and emitter regions;

forming said base and emitter regions through implantation; and

annealing said emitter regions at a temperature not exceeding 950 degrees Celsius.

2. A method according to claim 1 in which said temperature falls within a range of 800 to 850 degrees Celsius.

3. A method according to claim 2 in which said step of recrystalizing said silicon wafer is known as double solid-phase epitaxy.

4. A method according to claim 2 in which said silicon wafer has an interfacing surface adjacent said sapphire substrate and a surface opposite of said interfacing surface, in which said step of recrystalizing said silicon wafer includes:

amorphising said silicon wafer by the implantation of silicon in a region adjacent said interfacing surface, leaving a surface located non-amorphised region;

crystalizing said silicon wafer in an anneal using said surface located non-amorphised region as a recrystalization seed;

amorphising said silicon wafer by the implantation of silicon in a region adjacent said surface of said wafer, leaving an interfacing surface located non-amorphised region; and

crystalizing said silicon wafer in an anneal using said interfacing surface located non-amorphised region as a recrystalization seed.

5. A method according to claim 1 in which said step of recrystalizing said silicon wafer is known as double solid-phase epitaxy.

6. A method according to claim 1 in which said silicon wafer has an interfacing surface adjacent said sapphire substrate and a surface opposite of said interfacing surface, in which said step of recrystalizing said silicon wafer includes:

amorphising said silicon wafer by the implantation of silicon in a region adjacent said interfacing surface, leaving a surface located non-amorphised region;

crystalizing said silicon wafer in an anneal using said surface located non-amorphised region as a recrystalization seed;

amorphising said silicon wafer by the implantation of silicon in a region adjacent said surface of said wafer, leaving an interfacing surface located non-amorphised region; and

crystalizing said silicon wafer in an anneal using said interfacing surface located non-amorphised region as a recrystalization seed.

7. A method according to claim 6 in which said temperature falls within a range of 800 degrees Celsius to 850 degrees Celsius.

8. An improvement to a method for fabricating bipolar junction transistors in silicon-on-sapphire in which base and emitter regions are formed in a silicon wafer on top of a sapphire substrate, said silicon wafer having an interfacing surface adjacent said sapphire substrate and a surface opposite of said interfacing surface, the improvement including:

recrystalizing said silicon wafer prior to the formation of said base and emitter regions including the steps of;

amorphising said silicon wafer by the implantation of silicon in a region adjacent said interfacing surface, leaving a surface located non-amorphised region;

crystalizing said silicon wafer in an anneal using said surface located non-amorphised region as a recrystalization seed;

amorphising said silicon wafer by the implantation of silicon in a region adjacent said surface of said wafer, leaving an interfacing surface located non-amorphised region; and

crystalizing said silicon wafer in an anneal using said interfacing surface located non-amorphised region as a recrystalization seed;

forming said base and emitter regions through implantation; and

annealing said emitter regions at a temperature not exceeding 850 degrees Celsius.